1 /* 2 * Copyright (c) 2006-2022, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef __PCI_REGS_H__ 8 #define __PCI_REGS_H__ 9 10 #include <rtdef.h> 11 12 /* 13 * PCI standard defines 14 * Copyright 1994, Drew Eckhardt 15 * Copyright 1997--1999 Martin Mares <mj@ucw.cz> 16 * 17 * For more information, please consult the following manuals (look at 18 * http://www.pcisig.com/ for how to get them): 19 * 20 * PCI BIOS Specification 21 * PCI Local Bus Specification 22 * PCI to PCI Bridge Specification 23 * PCI System Design Guide 24 * 25 * For HyperTransport information, please consult the following manuals 26 * from http://www.hypertransport.org : 27 * 28 * The HyperTransport I/O Link Specification 29 * 30 * Mean of prefix: 31 * 32 * PCIM_xxx: mask to locate subfield in register 33 * PCIR_xxx: config register offset 34 * PCIC_xxx: device class 35 * PCIS_xxx: device subclass 36 * PCIP_xxx: device programming interface 37 * PCIV_xxx: PCI vendor ID (only required to fixup ancient devices) 38 * PCID_xxx: device ID 39 * PCIY_xxx: capability identification number 40 * PCIZ_xxx: extended capability identification number 41 */ 42 43 /* some PCI bus constants */ 44 #define PCI_DOMAINMAX 65535 /* highest supported domain number */ 45 #define PCI_BUSMAX 255 /* highest supported bus number */ 46 #define PCI_SLOTMAX 31 /* highest supported slot number */ 47 #define PCI_FUNCMAX 7 /* highest supported function number */ 48 #define PCI_REGMAX 255 /* highest supported config register addr */ 49 #define PCIE_REGMAX 4095 /* highest supported config register addr */ 50 #define PCI_MAXHDRTYPE 2 51 #define PCI_STD_HEADER_SIZEOF 64 52 #define PCI_STD_NUM_BARS 6 /* number of standard BARs */ 53 54 /* PCI config header registers for all devices */ 55 56 #define PCIR_DEVVENDOR 0x00 57 #define PCIR_VENDOR 0x00 58 #define PCIR_DEVICE 0x02 59 #define PCIR_COMMAND 0x04 60 #define PCIM_CMD_PORTEN 0x0001 61 #define PCIM_CMD_MEMEN 0x0002 62 #define PCIM_CMD_BUSMASTEREN 0x0004 63 #define PCIM_CMD_SPECIALEN 0x0008 64 #define PCIM_CMD_MWRICEN 0x0010 65 #define PCIM_CMD_PERRESPEN 0x0040 66 #define PCIM_CMD_SERRESPEN 0x0100 67 #define PCIM_CMD_BACKTOBACK 0x0200 68 #define PCIM_CMD_INTxDIS 0x0400 69 #define PCIR_STATUS 0x06 70 #define PCIM_STATUS_INTxSTATE 0x0008 71 #define PCIM_STATUS_CAPPRESENT 0x0010 72 #define PCIM_STATUS_66CAPABLE 0x0020 73 #define PCIM_STATUS_BACKTOBACK 0x0080 74 #define PCIM_STATUS_MDPERR 0x0100 75 #define PCIM_STATUS_SEL_FAST 0x0000 76 #define PCIM_STATUS_SEL_MEDIMUM 0x0200 77 #define PCIM_STATUS_SEL_SLOW 0x0400 78 #define PCIM_STATUS_SEL_MASK 0x0600 79 #define PCIM_STATUS_STABORT 0x0800 80 #define PCIM_STATUS_RTABORT 0x1000 81 #define PCIM_STATUS_RMABORT 0x2000 82 #define PCIM_STATUS_SERR 0x4000 83 #define PCIM_STATUS_PERR 0x8000 84 #define PCIR_REVID 0x08 85 #define PCIR_PROGIF 0x09 86 #define PCIR_SUBCLASS 0x0a 87 #define PCIR_CLASS 0x0b 88 #define PCIR_CACHELNSZ 0x0c 89 #define PCIR_LATTIMER 0x0d 90 #define PCIR_HDRTYPE 0x0e 91 #define PCIM_HDRTYPE 0x7f 92 #define PCIM_HDRTYPE_NORMAL 0x00 93 #define PCIM_HDRTYPE_BRIDGE 0x01 94 #define PCIM_HDRTYPE_CARDBUS 0x02 95 #define PCIM_MFDEV 0x80 96 #define PCIR_BIST 0x0f 97 98 /* PCI Spec rev 2.2: 0FFFFh is an invalid value for Vendor ID. */ 99 #define PCIV_INVALID 0xffff 100 101 /* Capability Register Offsets */ 102 103 #define PCICAP_ID 0x0 104 #define PCICAP_NEXTPTR 0x1 105 106 /* Capability Identification Numbers */ 107 108 #define PCIY_PMG 0x01 /* PCI Power Management */ 109 #define PCIY_AGP 0x02 /* AGP */ 110 #define PCIY_VPD 0x03 /* Vital Product Data */ 111 #define PCIY_SLOTID 0x04 /* Slot Identification */ 112 #define PCIY_MSI 0x05 /* Message Signaled Interrupts */ 113 #define PCIY_CHSWP 0x06 /* CompactPCI Hot Swap */ 114 #define PCIY_PCIX 0x07 /* PCI-X */ 115 #define PCIY_HT 0x08 /* HyperTransport */ 116 #define PCIY_VENDOR 0x09 /* Vendor Unique */ 117 #define PCIY_DEBUG 0x0a /* Debug port */ 118 #define PCIY_CRES 0x0b /* CompactPCI central resource control */ 119 #define PCIY_HOTPLUG 0x0c /* PCI Hot-Plug */ 120 #define PCIY_SUBVENDOR 0x0d /* PCI-PCI bridge subvendor ID */ 121 #define PCIY_AGP8X 0x0e /* AGP 8x */ 122 #define PCIY_SECDEV 0x0f /* Secure Device */ 123 #define PCIY_EXPRESS 0x10 /* PCI Express */ 124 #define PCIY_MSIX 0x11 /* MSI-X */ 125 #define PCIY_SATA 0x12 /* SATA */ 126 #define PCIY_PCIAF 0x13 /* PCI Advanced Features */ 127 #define PCIY_EA 0x14 /* PCI Extended Allocation */ 128 #define PCIY_FPB 0x15 /* Flattening Portal Bridge */ 129 #define PCIY_MAX PCIY_FPB 130 131 /* Extended Capability Register Fields */ 132 133 #define PCIR_EXTCAP 0x100 134 #define PCIM_EXTCAP_ID 0x0000ffff 135 #define PCIM_EXTCAP_VER 0x000f0000 136 #define PCIM_EXTCAP_NEXTPTR 0xfff00000 137 #define PCI_EXTCAP_ID(ecap) ((ecap) & PCIM_EXTCAP_ID) 138 #define PCI_EXTCAP_VER(ecap) (((ecap) & PCIM_EXTCAP_VER) >> 16) 139 #define PCI_EXTCAP_NEXTPTR(ecap) (((ecap) & PCIM_EXTCAP_NEXTPTR) >> 20) 140 141 /* Extended Capability Identification Numbers */ 142 143 #define PCIZ_AER 0x0001 /* Advanced Error Reporting */ 144 #define PCIZ_VC 0x0002 /* Virtual Channel if MFVC Ext Cap not set */ 145 #define PCIZ_SERNUM 0x0003 /* Device Serial Number */ 146 #define PCIZ_PWRBDGT 0x0004 /* Power Budgeting */ 147 #define PCIZ_RCLINK_DCL 0x0005 /* Root Complex Link Declaration */ 148 #define PCIZ_RCLINK_CTL 0x0006 /* Root Complex Internal Link Control */ 149 #define PCIZ_RCEC_ASSOC 0x0007 /* Root Complex Event Collector Association */ 150 #define PCIZ_MFVC 0x0008 /* Multi-Function Virtual Channel */ 151 #define PCIZ_VC2 0x0009 /* Virtual Channel if MFVC Ext Cap set */ 152 #define PCIZ_RCRB 0x000a /* RCRB Header */ 153 #define PCIZ_VENDOR 0x000b /* Vendor Unique */ 154 #define PCIZ_CAC 0x000c /* Configuration Access Correction -- obsolete */ 155 #define PCIZ_ACS 0x000d /* Access Control Services */ 156 #define PCIZ_ARI 0x000e /* Alternative Routing-ID Interpretation */ 157 #define PCIZ_ATS 0x000f /* Address Translation Services */ 158 #define PCIZ_SRIOV 0x0010 /* Single Root IO Virtualization */ 159 #define PCIZ_MRIOV 0x0011 /* Multiple Root IO Virtualization */ 160 #define PCIZ_MULTICAST 0x0012 /* Multicast */ 161 #define PCIZ_PAGE_REQ 0x0013 /* Page Request */ 162 #define PCIZ_AMD 0x0014 /* Reserved for AMD */ 163 #define PCIZ_RESIZE_BAR 0x0015 /* Resizable BAR */ 164 #define PCIZ_DPA 0x0016 /* Dynamic Power Allocation */ 165 #define PCIZ_TPH_REQ 0x0017 /* TPH Requester */ 166 #define PCIZ_LTR 0x0018 /* Latency Tolerance Reporting */ 167 #define PCIZ_SEC_PCIE 0x0019 /* Secondary PCI Express */ 168 #define PCIZ_PMUX 0x001a /* Protocol Multiplexing */ 169 #define PCIZ_PASID 0x001b /* Process Address Space ID */ 170 #define PCIZ_LN_REQ 0x001c /* LN Requester */ 171 #define PCIZ_DPC 0x001d /* Downstream Port Containment */ 172 #define PCIZ_L1PM 0x001e /* L1 PM Substates */ 173 #define PCIZ_PTM 0x001f /* Precision Time Measurement */ 174 #define PCIZ_M_PCIE 0x0020 /* PCIe over M-PHY */ 175 #define PCIZ_FRS 0x0021 /* FRS Queuing */ 176 #define PCIZ_RTR 0x0022 /* Readiness Time Reporting */ 177 #define PCIZ_DVSEC 0x0023 /* Designated Vendor-Specific */ 178 #define PCIZ_VF_REBAR 0x0024 /* VF Resizable BAR */ 179 #define PCIZ_DLNK 0x0025 /* Data Link Feature */ 180 #define PCIZ_16GT 0x0026 /* Physical Layer 16.0 GT/s */ 181 #define PCIZ_LMR 0x0027 /* Lane Margining at Receiver */ 182 #define PCIZ_HIER_ID 0x0028 /* Hierarchy ID */ 183 #define PCIZ_NPEM 0x0029 /* Native PCIe Enclosure Management */ 184 #define PCIZ_PL32 0x002a /* Physical Layer 32.0 GT/s */ 185 #define PCIZ_AP 0x002b /* Alternate Protocol */ 186 #define PCIZ_SFI 0x002c /* System Firmware Intermediary */ 187 188 /* Resizable BARs */ 189 #define PCIM_REBAR_CAP 4 /* Capability register */ 190 #define PCIM_REBAR_CAP_SIZES 0x00fffff0 /* Supported BAR sizes */ 191 #define PCIM_REBAR_CTRL 8 /* Control register */ 192 #define PCIM_REBAR_CTRL_BAR_IDX 0x00000007 /* BAR index */ 193 #define PCIM_REBAR_CTRL_NBAR_MASK 0x000000e0 194 #define PCIM_REBAR_CTRL_NBAR_SHIFT 5 /* Shift for # of BARs */ 195 #define PCIM_REBAR_CTRL_BAR_SIZE 0x00001f00 /* BAR size */ 196 #define PCIM_REBAR_CTRL_BAR_SHIFT 8 /* Shift for BAR size */ 197 198 /* config registers for header type 0 devices */ 199 200 #define PCIR_BARS 0x10 201 #define PCIR_BAR(x) (PCIR_BARS + (x) * 4) 202 #define PCI_RID2BAR(rid) (((rid) - PCIR_BARS) / 4) 203 #define PCI_BAR_IO(x) (((x) & PCIM_BAR_SPACE) == PCIM_BAR_IO_SPACE) 204 #define PCI_BAR_MEM(x) (((x) & PCIM_BAR_SPACE) == PCIM_BAR_MEM_SPACE) 205 #define PCIM_BAR_SPACE 0x01 /* 0 = memory, 1 = I/O */ 206 #define PCIM_BAR_SPACE_IO 0x01 207 #define PCIM_BAR_SPACE_MEMORY 0x00 208 #define PCIM_BAR_MEM_TYPE_MASK 0x06 209 #define PCIM_BAR_MEM_TYPE_32 0x00 /* 32 bit address */ 210 #define PCIM_BAR_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */ 211 #define PCIM_BAR_MEM_TYPE_64 0x04 /* 64 bit address */ 212 #define PCIM_BAR_MEM_PREFETCH 0x08 /* prefetchable? */ 213 #define PCIM_BAR_MEM_MASK (~0x0fUL) 214 #define PCIM_BAR_IO_MASK (~0x03UL) 215 #define PCIR_CIS 0x28 216 #define PCIM_CIS_ASI_MASK 0x00000007 217 #define PCIM_CIS_ASI_CONFIG 0 218 #define PCIM_CIS_ASI_BAR0 1 219 #define PCIM_CIS_ASI_BAR1 2 220 #define PCIM_CIS_ASI_BAR2 3 221 #define PCIM_CIS_ASI_BAR3 4 222 #define PCIM_CIS_ASI_BAR4 5 223 #define PCIM_CIS_ASI_BAR5 6 224 #define PCIM_CIS_ASI_ROM 7 225 #define PCIM_CIS_ADDR_MASK 0x0ffffff8 226 #define PCIM_CIS_ROM_MASK 0xf0000000 227 #define PCIM_CIS_CONFIG_MASK 0xff 228 #define PCIR_SUBVEND_0 0x2c 229 #define PCIR_SUBDEV_0 0x2e 230 #define PCIR_BIOS 0x30 231 #define PCIM_BIOS_ENABLE 0x01 232 #define PCIM_BIOS_ADDR_MASK 0xfffff800 233 #define PCIR_CAP_PTR 0x34 234 #define PCIR_INTLINE 0x3c 235 #define PCIR_INTPIN 0x3d 236 #define PCIR_MINGNT 0x3e 237 #define PCIR_MAXLAT 0x3f 238 239 /* config registers for header type 1 (PCI-to-PCI bridge) devices */ 240 241 #define PCIR_MAX_BAR_1 1 242 #define PCIR_SECSTAT_1 0x1e 243 244 #define PCIR_PRIBUS_1 0x18 245 #define PCIR_SECBUS_1 0x19 246 #define PCIR_SUBBUS_1 0x1a 247 #define PCIR_SECLAT_1 0x1b 248 249 #define PCIR_IOBASEL_1 0x1c 250 #define PCIR_IOLIMITL_1 0x1d 251 #define PCIR_IOBASEH_1 0x30 252 #define PCIR_IOLIMITH_1 0x32 253 #define PCIM_BRIO_16 0x0 254 #define PCIM_BRIO_32 0x1 255 #define PCIM_BRIO_MASK 0xf 256 257 #define PCIR_MEMBASE_1 0x20 258 #define PCIR_MEMLIMIT_1 0x22 259 260 #define PCIR_PMBASEL_1 0x24 261 #define PCIR_PMLIMITL_1 0x26 262 #define PCIR_PMBASEH_1 0x28 263 #define PCIR_PMLIMITH_1 0x2c 264 #define PCIM_BRPM_32 0x0 265 #define PCIM_BRPM_64 0x1 266 #define PCIM_BRPM_MASK 0xf 267 268 #define PCIR_BIOS_1 0x38 269 #define PCIR_BRIDGECTL_1 0x3e 270 271 #define PCI_PPBMEMBASE(h, l) ((((rt_uint64_t)(h) << 32) + ((l) << 16)) & ~0xfffff) 272 #define PCI_PPBMEMLIMIT(h, l) ((((rt_uint64_t)(h) << 32) + ((l) << 16)) | 0xfffff) 273 #define PCI_PPBIOBASE(h, l) ((((h) << 16) + ((l) << 8)) & ~0xfff) 274 #define PCI_PPBIOLIMIT(h, l) ((((h) << 16) + ((l) << 8)) | 0xfff) 275 276 /* config registers for header t ype 2 (CardBus) devices */ 277 278 #define PCIR_MAX_BAR_2 0 279 #define PCIR_CAP_PTR_2 0x14 280 #define PCIR_SECSTAT_2 0x16 281 282 #define PCIR_PRIBUS_2 0x18 283 #define PCIR_SECBUS_2 0x19 284 #define PCIR_SUBBUS_2 0x1a 285 #define PCIR_SECLAT_2 0x1b 286 287 #define PCIR_MEMBASE0_2 0x1c 288 #define PCIR_MEMLIMIT0_2 0x20 289 #define PCIR_MEMBASE1_2 0x24 290 #define PCIR_MEMLIMIT1_2 0x28 291 #define PCIR_IOBASE0_2 0x2c 292 #define PCIR_IOLIMIT0_2 0x30 293 #define PCIR_IOBASE1_2 0x34 294 #define PCIR_IOLIMIT1_2 0x38 295 #define PCIM_CBBIO_16 0x0 296 #define PCIM_CBBIO_32 0x1 297 #define PCIM_CBBIO_MASK 0x3 298 299 #define PCIR_BRIDGECTL_2 0x3e 300 301 #define PCIR_SUBVEND_2 0x40 302 #define PCIR_SUBDEV_2 0x42 303 304 #define PCIR_PCCARDIF_2 0x44 305 306 #define PCI_CBBMEMBASE(l) ((l) & ~0xfffff) 307 #define PCI_CBBMEMLIMIT(l) ((l) | 0xfffff) 308 #define PCI_CBBIOBASE(l) ((l) & ~0x3) 309 #define PCI_CBBIOLIMIT(l) ((l) | 0x3) 310 311 /* PCI device class, subclass and programming interface definitions */ 312 #define PCIC_NOT_DEFINED 0x0000 313 #define PCIS_NOT_DEFINED_VGA 0x0001 314 315 #define PCIC_STORAGE 0x01 316 #define PCIS_STORAGE_SCSI 0x0100 317 #define PCIS_STORAGE_IDE 0x0101 318 #define PCIS_STORAGE_FLOPPY 0x0102 319 #define PCIS_STORAGE_IPI 0x0103 320 #define PCIS_STORAGE_RAID 0x0104 321 #define PCIS_STORAGE_SATA 0x0106 322 #define PCIS_STORAGE_SATA_AHCI 0x010601 323 #define PCIS_STORAGE_SAS 0x0107 324 #define PCIS_STORAGE_EXPRESS 0x010802 325 #define PCIS_STORAGE_OTHER 0x0180 326 327 #define PCIC_NETWORK 0x02 328 #define PCIS_NETWORK_ETHERNET 0x0200 329 #define PCIS_NETWORK_TOKEN_RING 0x0201 330 #define PCIS_NETWORK_FDDI 0x0202 331 #define PCIS_NETWORK_ATM 0x0203 332 #define PCIS_NETWORK_OTHER 0x0280 333 334 #define PCIC_DISPLAY 0x03 335 #define PCIS_DISPLAY_VGA 0x0300 336 #define PCIS_DISPLAY_XGA 0x0301 337 #define PCIS_DISPLAY_3D 0x0302 338 #define PCIS_DISPLAY_OTHER 0x0380 339 340 #define PCIC_MULTIMEDIA 0x04 341 #define PCIS_MULTIMEDIA_VIDEO 0x0400 342 #define PCIS_MULTIMEDIA_AUDIO 0x0401 343 #define PCIS_MULTIMEDIA_PHONE 0x0402 344 #define PCIS_MULTIMEDIA_HD_AUDIO 0x0403 345 #define PCIS_MULTIMEDIA_OTHER 0x0480 346 347 #define PCIC_MEMORY 0x05 348 #define PCIS_MEMORY_RAM 0x0500 349 #define PCIS_MEMORY_FLASH 0x0501 350 #define PCIS_MEMORY_CXL 0x0502 351 #define PCIS_MEMORY_OTHER 0x0580 352 353 #define PCIC_BRIDGE 0x06 354 #define PCIS_BRIDGE_HOST 0x0600 355 #define PCIS_BRIDGE_ISA 0x0601 356 #define PCIS_BRIDGE_EISA 0x0602 357 #define PCIS_BRIDGE_MC 0x0603 358 #define PCIS_BRIDGE_PCI 0x0604 359 #define PCIS_BRIDGE_PCI_NORMAL 0x060400 360 #define PCIS_BRIDGE_PCI_SUBTRACTIVE 0x060401 361 #define PCIS_BRIDGE_PCMCIA 0x0605 362 #define PCIS_BRIDGE_NUBUS 0x0606 363 #define PCIS_BRIDGE_CARDBUS 0x0607 364 #define PCIS_BRIDGE_RACEWAY 0x0608 365 #define PCIS_BRIDGE_OTHER 0x0680 366 367 #define PCIC_COMMUNICATION 0x07 368 #define PCIS_COMMUNICATION_SERIAL 0x0700 369 #define PCIS_COMMUNICATION_PARALLEL 0x0701 370 #define PCIS_COMMUNICATION_MULTISERIAL 0x0702 371 #define PCIS_COMMUNICATION_MODEM 0x0703 372 #define PCIS_COMMUNICATION_OTHER 0x0780 373 374 #define PCIC_SYSTEM 0x08 375 #define PCIS_SYSTEM_PIC 0x0800 376 #define PCIS_SYSTEM_PIC_IOAPIC 0x080010 377 #define PCIS_SYSTEM_PIC_IOXAPIC 0x080020 378 #define PCIS_SYSTEM_DMA 0x0801 379 #define PCIS_SYSTEM_TIMER 0x0802 380 #define PCIS_SYSTEM_RTC 0x0803 381 #define PCIS_SYSTEM_PCI_HOTPLUG 0x0804 382 #define PCIS_SYSTEM_SDHCI 0x0805 383 #define PCIS_SYSTEM_RCEC 0x0807 384 #define PCIS_SYSTEM_OTHER 0x0880 385 386 #define PCIC_INPUT 0x09 387 #define PCIS_INPUT_KEYBOARD 0x0900 388 #define PCIS_INPUT_PEN 0x0901 389 #define PCIS_INPUT_MOUSE 0x0902 390 #define PCIS_INPUT_SCANNER 0x0903 391 #define PCIS_INPUT_GAMEPORT 0x0904 392 #define PCIS_INPUT_OTHER 0x0980 393 394 #define PCIC_DOCKING 0x0a 395 #define PCIS_DOCKING_GENERIC 0x0a00 396 #define PCIS_DOCKING_OTHER 0x0a80 397 398 #define PCIC_PROCESSOR 0x0b 399 #define PCIS_PROCESSOR_386 0x0b00 400 #define PCIS_PROCESSOR_486 0x0b01 401 #define PCIS_PROCESSOR_PENTIUM 0x0b02 402 #define PCIS_PROCESSOR_ALPHA 0x0b10 403 #define PCIS_PROCESSOR_POWERPC 0x0b20 404 #define PCIS_PROCESSOR_MIPS 0x0b30 405 #define PCIS_PROCESSOR_CO 0x0b40 406 407 #define PCIC_SERIAL 0x0c 408 #define PCIS_SERIAL_FIREWIRE 0x0c00 409 #define PCIS_SERIAL_FIREWIRE_OHCI 0x0c0010 410 #define PCIS_SERIAL_ACCESS 0x0c01 411 #define PCIS_SERIAL_SSA 0x0c02 412 #define PCIS_SERIAL_USB 0x0c03 413 #define PCIS_SERIAL_USB_UHCI 0x0c0300 414 #define PCIS_SERIAL_USB_OHCI 0x0c0310 415 #define PCIS_SERIAL_USB_EHCI 0x0c0320 416 #define PCIS_SERIAL_USB_XHCI 0x0c0330 417 #define PCIS_SERIAL_USB_DEVICE 0x0c03fe 418 #define PCIS_SERIAL_FIBER 0x0c04 419 #define PCIS_SERIAL_SMBUS 0x0c05 420 #define PCIS_SERIAL_IPMI 0x0c07 421 #define PCIS_SERIAL_IPMI_SMIC 0x0c0700 422 #define PCIS_SERIAL_IPMI_KCS 0x0c0701 423 #define PCIS_SERIAL_IPMI_BT 0x0c0702 424 425 #define PCIC_WIRELESS 0x0d 426 #define PCIS_WIRELESS_RF_CONTROLLER 0x0d10 427 #define PCIS_WIRELESS_WHCI 0x0d1010 428 429 #define PCIC_INTELLIGENT 0x0e 430 #define PCIS_INTELLIGENT_I2O 0x0e00 431 432 #define PCIC_SATELLITE 0x0f 433 #define PCIS_SATELLITE_TV 0x0f00 434 #define PCIS_SATELLITE_AUDIO 0x0f01 435 #define PCIS_SATELLITE_VOICE 0x0f03 436 #define PCIS_SATELLITE_DATA 0x0f04 437 438 #define PCIC_CRYPT 0x10 439 #define PCIS_CRYPT_NETWORK 0x1000 440 #define PCIS_CRYPT_ENTERTAINMENT 0x1001 441 #define PCIS_CRYPT_OTHER 0x1080 442 443 #define PCIC_SIGNAL_PROCESSING 0x11 444 #define PCIS_SP_DPIO 0x1100 445 #define PCIS_SP_OTHER 0x1180 446 447 #define PCIS_OTHERS 0xff 448 449 /* Bridge Control Values. */ 450 #define PCIB_BCR_PERR_ENABLE 0x0001 451 #define PCIB_BCR_SERR_ENABLE 0x0002 452 #define PCIB_BCR_ISA_ENABLE 0x0004 453 #define PCIB_BCR_VGA_ENABLE 0x0008 454 #define PCIB_BCR_MASTER_ABORT_MODE 0x0020 455 #define PCIB_BCR_SECBUS_RESET 0x0040 456 #define PCIB_BCR_SECBUS_BACKTOBACK 0x0080 457 #define PCIB_BCR_PRI_DISCARD_TIMEOUT 0x0100 458 #define PCIB_BCR_SEC_DISCARD_TIMEOUT 0x0200 459 #define PCIB_BCR_DISCARD_TIMER_STATUS 0x0400 460 #define PCIB_BCR_DISCARD_TIMER_SERREN 0x0800 461 462 #define CBB_BCR_PERR_ENABLE 0x0001 463 #define CBB_BCR_SERR_ENABLE 0x0002 464 #define CBB_BCR_ISA_ENABLE 0x0004 465 #define CBB_BCR_VGA_ENABLE 0x0008 466 #define CBB_BCR_MASTER_ABORT_MODE 0x0020 467 #define CBB_BCR_CARDBUS_RESET 0x0040 468 #define CBB_BCR_IREQ_INT_ENABLE 0x0080 469 #define CBB_BCR_PREFETCH_0_ENABLE 0x0100 470 #define CBB_BCR_PREFETCH_1_ENABLE 0x0200 471 #define CBB_BCR_WRITE_POSTING_ENABLE 0x0400 472 473 /* PCI power manangement */ 474 #define PCIR_POWER_CAP 0x2 475 #define PCIM_PCAP_SPEC 0x0007 476 #define PCIM_PCAP_PMEREQCLK 0x0008 477 #define PCIM_PCAP_DEVSPECINIT 0x0020 478 #define PCIM_PCAP_AUXPWR_0 0x0000 479 #define PCIM_PCAP_AUXPWR_55 0x0040 480 #define PCIM_PCAP_AUXPWR_100 0x0080 481 #define PCIM_PCAP_AUXPWR_160 0x00c0 482 #define PCIM_PCAP_AUXPWR_220 0x0100 483 #define PCIM_PCAP_AUXPWR_270 0x0140 484 #define PCIM_PCAP_AUXPWR_320 0x0180 485 #define PCIM_PCAP_AUXPWR_375 0x01c0 486 #define PCIM_PCAP_AUXPWRMASK 0x01c0 487 #define PCIM_PCAP_D1SUPP 0x0200 488 #define PCIM_PCAP_D2SUPP 0x0400 489 #define PCIM_PCAP_PMEMASK 0xf800 490 #define PCIM_PCAP_D0PME 0x0800 491 #define PCIM_PCAP_D1PME 0x1000 492 #define PCIM_PCAP_D2PME 0x2000 493 #define PCIM_PCAP_D3PME_HOT 0x4000 494 #define PCIM_PCAP_D3PME_COLD 0x8000 495 496 #define PCIR_POWER_STATUS 0x4 497 #define PCIM_PSTAT_D0 0x0000 498 #define PCIM_PSTAT_D1 0x0001 499 #define PCIM_PSTAT_D2 0x0002 500 #define PCIM_PSTAT_D3 0x0003 501 #define PCIM_PSTAT_DMASK 0x0003 502 #define PCIM_PSTAT_NOSOFTRESET 0x0008 503 #define PCIM_PSTAT_PMEENABLE 0x0100 504 #define PCIM_PSTAT_D0POWER 0x0000 505 #define PCIM_PSTAT_D1POWER 0x0200 506 #define PCIM_PSTAT_D2POWER 0x0400 507 #define PCIM_PSTAT_D3POWER 0x0600 508 #define PCIM_PSTAT_D0HEAT 0x0800 509 #define PCIM_PSTAT_D1HEAT 0x0a00 510 #define PCIM_PSTAT_D2HEAT 0x0c00 511 #define PCIM_PSTAT_D3HEAT 0x0e00 512 #define PCIM_PSTAT_DATASELMASK 0x1e00 513 #define PCIM_PSTAT_DATAUNKN 0x0000 514 #define PCIM_PSTAT_DATADIV10 0x2000 515 #define PCIM_PSTAT_DATADIV100 0x4000 516 #define PCIM_PSTAT_DATADIV1000 0x6000 517 #define PCIM_PSTAT_DATADIVMASK 0x6000 518 #define PCIM_PSTAT_PME 0x8000 519 520 #define PCIR_POWER_BSE 0x6 521 #define PCIM_PMCSR_BSE_D3B3 0x00 522 #define PCIM_PMCSR_BSE_D3B2 0x40 523 #define PCIM_PMCSR_BSE_BPCCE 0x80 524 525 #define PCIR_POWER_DATA 0x7 526 527 /* VPD capability registers */ 528 #define PCIR_VPD_ADDR 0x2 529 #define PCIR_VPD_DATA 0x4 530 531 /* PCI Message Signalled Interrupts (MSI) */ 532 #define PCIR_MSI_CTRL 0x2 533 #define PCIM_MSICTRL_VECTOR 0x0100 534 #define PCIM_MSICTRL_64BIT 0x0080 535 #define PCIM_MSICTRL_MME_MASK 0x0070 536 #define PCIM_MSICTRL_MME_SHIFT 0x4 537 #define PCIM_MSICTRL_MME_1 0x0000 538 #define PCIM_MSICTRL_MME_2 0x0010 539 #define PCIM_MSICTRL_MME_4 0x0020 540 #define PCIM_MSICTRL_MME_8 0x0030 541 #define PCIM_MSICTRL_MME_16 0x0040 542 #define PCIM_MSICTRL_MME_32 0x0050 543 #define PCIM_MSICTRL_MMC_MASK 0x000e 544 #define PCIM_MSICTRL_MMC_SHIFT 0x1 545 #define PCIM_MSICTRL_MMC_1 0x0000 546 #define PCIM_MSICTRL_MMC_2 0x0002 547 #define PCIM_MSICTRL_MMC_4 0x0004 548 #define PCIM_MSICTRL_MMC_8 0x0006 549 #define PCIM_MSICTRL_MMC_16 0x0008 550 #define PCIM_MSICTRL_MMC_32 0x000a 551 #define PCIM_MSICTRL_MSI_ENABLE 0x0001 552 #define PCIR_MSI_ADDR 0x4 553 #define PCIR_MSI_ADDR_HIGH 0x8 554 #define PCIR_MSI_DATA 0x8 555 #define PCIR_MSI_DATA_64BIT 0xc 556 #define PCIR_MSI_MASK 0xc 557 #define PCIR_MSI_MASK_64BIT 0x10 558 #define PCIR_MSI_PENDING 0x14 559 560 /* PCI Enhanced Allocation registers */ 561 #define PCIR_EA_NUM_ENT 2 /* Number of Capability Entries */ 562 #define PCIM_EA_NUM_ENT_MASK 0x3f /* Num Entries Mask */ 563 #define PCIR_EA_FIRST_ENT 4 /* First EA Entry in List */ 564 #define PCIR_EA_FIRST_ENT_BRIDGE 8 /* First EA Entry for Bridges */ 565 #define PCIM_EA_ES 0x00000007 /* Entry Size */ 566 #define PCIM_EA_BEI 0x000000f0 /* BAR Equivalent Indicator */ 567 #define PCIM_EA_BEI_OFFSET 4 568 /* 0-5 map to BARs 0-5 respectively */ 569 #define PCIM_EA_BEI_BAR_0 0 570 #define PCIM_EA_BEI_BAR_5 5 571 #define PCIM_EA_BEI_BAR(x) (((x) >> PCIM_EA_BEI_OFFSET) & 0xf) 572 #define PCIM_EA_BEI_BRIDGE 0x6 /* Resource behind bridge */ 573 #define PCIM_EA_BEI_ENI 0x7 /* Equivalent Not Indicated */ 574 #define PCIM_EA_BEI_ROM 0x8 /* Expansion ROM */ 575 /* 9-14 map to VF BARs 0-5 respectively */ 576 #define PCIM_EA_BEI_VF_BAR_0 9 577 #define PCIM_EA_BEI_VF_BAR_5 14 578 #define PCIM_EA_BEI_RESERVED 0xf /* Reserved - Treat like ENI */ 579 #define PCIM_EA_PP 0x0000ff00 /* Primary Properties */ 580 #define PCIM_EA_PP_OFFSET 8 581 #define PCIM_EA_SP_OFFSET 16 582 #define PCIM_EA_SP 0x00ff0000 /* Secondary Properties */ 583 #define PCIM_EA_P_MEM 0x00 /* Non-Prefetch Memory */ 584 #define PCIM_EA_P_MEM_PREFETCH 0x01 /* Prefetchable Memory */ 585 #define PCIM_EA_P_IO 0x02 /* I/O Space */ 586 #define PCIM_EA_P_VF_MEM_PREFETCH 0x03 /* VF Prefetchable Memory */ 587 #define PCIM_EA_P_VF_MEM 0x04 /* VF Non-Prefetch Memory */ 588 #define PCIM_EA_P_BRIDGE_MEM 0x05 /* Bridge Non-Prefetch Memory */ 589 #define PCIM_EA_P_BRIDGE_MEM_PREFETCH 0x06 /* Bridge Prefetchable Memory */ 590 #define PCIM_EA_P_BRIDGE_IO 0x07 /* Bridge I/O Space */ 591 /* 0x08-0xfc reserved */ 592 #define PCIM_EA_P_MEM_RESERVED 0xfd /* Reserved Memory */ 593 #define PCIM_EA_P_IO_RESERVED 0xfe /* Reserved I/O Space */ 594 #define PCIM_EA_P_UNAVAILABLE 0xff /* Entry Unavailable */ 595 #define PCIM_EA_WRITABLE 0x40000000 /* Writable: 1 = RW, 0 = HwInit */ 596 #define PCIM_EA_ENABLE 0x80000000 /* Enable for this entry */ 597 #define PCIM_EA_BASE 4 /* Base Address Offset */ 598 #define PCIM_EA_MAX_OFFSET 8 /* MaxOffset (resource length) */ 599 /* bit 0 is reserved */ 600 #define PCIM_EA_IS_64 0x00000002 /* 64-bit field flag */ 601 #define PCIM_EA_FIELD_MASK 0xfffffffc /* For Base & Max Offset */ 602 /* Bridge config register */ 603 #define PCIM_EA_SEC_NR(reg) ((reg) & 0xff) 604 #define PCIM_EA_SUB_NR(reg) (((reg) >> 8) & 0xff) 605 606 /* PCI-X definitions */ 607 608 /* For header type 0 devices */ 609 #define PCIXR_COMMAND 0x2 610 #define PCIXM_COMMAND_DPERR_E 0x0001 /* Data Parity Error Recovery */ 611 #define PCIXM_COMMAND_ERO 0x0002 /* Enable Relaxed Ordering */ 612 #define PCIXM_COMMAND_MAX_READ 0x000c /* Maximum Burst Read Count */ 613 #define PCIXM_COMMAND_MAX_READ_512 0x0000 614 #define PCIXM_COMMAND_MAX_READ_1024 0x0004 615 #define PCIXM_COMMAND_MAX_READ_2048 0x0008 616 #define PCIXM_COMMAND_MAX_READ_4096 0x000c 617 #define PCIXM_COMMAND_MAX_SPLITS 0x0070 /* Maximum Split Transactions */ 618 #define PCIXM_COMMAND_MAX_SPLITS_1 0x0000 619 #define PCIXM_COMMAND_MAX_SPLITS_2 0x0010 620 #define PCIXM_COMMAND_MAX_SPLITS_3 0x0020 621 #define PCIXM_COMMAND_MAX_SPLITS_4 0x0030 622 #define PCIXM_COMMAND_MAX_SPLITS_8 0x0040 623 #define PCIXM_COMMAND_MAX_SPLITS_12 0x0050 624 #define PCIXM_COMMAND_MAX_SPLITS_16 0x0060 625 #define PCIXM_COMMAND_MAX_SPLITS_32 0x0070 626 #define PCIXM_COMMAND_VERSION 0x3000 627 #define PCIXR_STATUS 0x4 628 #define PCIXM_STATUS_DEVFN 0x000000ff 629 #define PCIXM_STATUS_BUS 0x0000ff00 630 #define PCIXM_STATUS_64BIT 0x00010000 631 #define PCIXM_STATUS_133CAP 0x00020000 632 #define PCIXM_STATUS_SC_DISCARDED 0x00040000 633 #define PCIXM_STATUS_UNEXP_SC 0x00080000 634 #define PCIXM_STATUS_COMPLEX_DEV 0x00100000 635 #define PCIXM_STATUS_MAX_READ 0x00600000 636 #define PCIXM_STATUS_MAX_READ_512 0x00000000 637 #define PCIXM_STATUS_MAX_READ_1024 0x00200000 638 #define PCIXM_STATUS_MAX_READ_2048 0x00400000 639 #define PCIXM_STATUS_MAX_READ_4096 0x00600000 640 #define PCIXM_STATUS_MAX_SPLITS 0x03800000 641 #define PCIXM_STATUS_MAX_SPLITS_1 0x00000000 642 #define PCIXM_STATUS_MAX_SPLITS_2 0x00800000 643 #define PCIXM_STATUS_MAX_SPLITS_3 0x01000000 644 #define PCIXM_STATUS_MAX_SPLITS_4 0x01800000 645 #define PCIXM_STATUS_MAX_SPLITS_8 0x02000000 646 #define PCIXM_STATUS_MAX_SPLITS_12 0x02800000 647 #define PCIXM_STATUS_MAX_SPLITS_16 0x03000000 648 #define PCIXM_STATUS_MAX_SPLITS_32 0x03800000 649 #define PCIXM_STATUS_MAX_CUM_READ 0x1c000000 650 #define PCIXM_STATUS_RCVD_SC_ERR 0x20000000 651 #define PCIXM_STATUS_266CAP 0x40000000 652 #define PCIXM_STATUS_533CAP 0x80000000 653 654 /* For header type 1 devices (PCI-X bridges) */ 655 #define PCIXR_SEC_STATUS 0x2 656 #define PCIXM_SEC_STATUS_64BIT 0x0001 657 #define PCIXM_SEC_STATUS_133CAP 0x0002 658 #define PCIXM_SEC_STATUS_SC_DISC 0x0004 659 #define PCIXM_SEC_STATUS_UNEXP_SC 0x0008 660 #define PCIXM_SEC_STATUS_SC_OVERRUN 0x0010 661 #define PCIXM_SEC_STATUS_SR_DELAYED 0x0020 662 #define PCIXM_SEC_STATUS_BUS_MODE 0x03c0 663 #define PCIXM_SEC_STATUS_VERSION 0x3000 664 #define PCIXM_SEC_STATUS_266CAP 0x4000 665 #define PCIXM_SEC_STATUS_533CAP 0x8000 666 #define PCIXR_BRIDGE_STATUS 0x4 667 #define PCIXM_BRIDGE_STATUS_DEVFN 0x000000ff 668 #define PCIXM_BRIDGE_STATUS_BUS 0x0000ff00 669 #define PCIXM_BRIDGE_STATUS_64BIT 0x00010000 670 #define PCIXM_BRIDGE_STATUS_133CAP 0x00020000 671 #define PCIXM_BRIDGE_STATUS_SC_DISCARDED 0x00040000 672 #define PCIXM_BRIDGE_STATUS_UNEXP_SC 0x00080000 673 #define PCIXM_BRIDGE_STATUS_SC_OVERRUN 0x00100000 674 #define PCIXM_BRIDGE_STATUS_SR_DELAYED 0x00200000 675 #define PCIXM_BRIDGE_STATUS_DEVID_MSGCAP 0x20000000 676 #define PCIXM_BRIDGE_STATUS_266CAP 0x40000000 677 #define PCIXM_BRIDGE_STATUS_533CAP 0x80000000 678 679 /* HT (HyperTransport) Capability definitions */ 680 #define PCIR_HT_COMMAND 0x2 681 #define PCIM_HTCMD_CAP_MASK 0xf800 /* Capability type. */ 682 #define PCIM_HTCAP_SLAVE 0x0000 /* 000xx */ 683 #define PCIM_HTCAP_HOST 0x2000 /* 001xx */ 684 #define PCIM_HTCAP_SWITCH 0x4000 /* 01000 */ 685 #define PCIM_HTCAP_INTERRUPT 0x8000 /* 10000 */ 686 #define PCIM_HTCAP_REVISION_ID 0x8800 /* 10001 */ 687 #define PCIM_HTCAP_UNITID_CLUMPING 0x9000 /* 10010 */ 688 #define PCIM_HTCAP_EXT_CONFIG_SPACE 0x9800 /* 10011 */ 689 #define PCIM_HTCAP_ADDRESS_MAPPING 0xa000 /* 10100 */ 690 #define PCIM_HTCAP_MSI_MAPPING 0xa800 /* 10101 */ 691 #define PCIM_HTCAP_DIRECT_ROUTE 0xb000 /* 10110 */ 692 #define PCIM_HTCAP_VCSET 0xb800 /* 10111 */ 693 #define PCIM_HTCAP_RETRY_MODE 0xc000 /* 11000 */ 694 #define PCIM_HTCAP_X86_ENCODING 0xc800 /* 11001 */ 695 #define PCIM_HTCAP_GEN3 0xd000 /* 11010 */ 696 #define PCIM_HTCAP_FLE 0xd800 /* 11011 */ 697 #define PCIM_HTCAP_PM 0xe000 /* 11100 */ 698 #define PCIM_HTCAP_HIGH_NODE_COUNT 0xe800 /* 11101 */ 699 700 /* HT MSI Mapping Capability definitions. */ 701 #define PCIM_HTCMD_MSI_ENABLE 0x0001 702 #define PCIM_HTCMD_MSI_FIXED 0x0002 703 #define PCIR_HTMSI_ADDRESS_LO 0x4 704 #define PCIR_HTMSI_ADDRESS_HI 0x8 705 706 /* PCI Vendor capability definitions */ 707 #define PCIR_VENDOR_LENGTH 0x2 708 #define PCIR_VENDOR_DATA 0x3 709 710 /* PCI Device capability definitions */ 711 #define PCIR_DEVICE_LENGTH 0x2 712 713 /* PCI EHCI Debug Port definitions */ 714 #define PCIR_DEBUG_PORT 0x2 715 #define PCIM_DEBUG_PORT_OFFSET 0x1fff 716 #define PCIM_DEBUG_PORT_BAR 0xe000 717 718 /* PCI-PCI Bridge Subvendor definitions */ 719 #define PCIR_SUBVENDCAP_ID 0x4 720 #define PCIR_SUBVENDCAP 0x4 721 #define PCIR_SUBDEVCAP 0x6 722 723 /* PCI Express definitions */ 724 #define PCIER_FLAGS 0x2 725 #define PCIEM_FLAGS_VERSION 0x000f 726 #define PCIEM_FLAGS_TYPE 0x00f0 727 #define PCIEM_TYPE_ENDPOINT 0x0000 728 #define PCIEM_TYPE_LEGACY_ENDPOINT 0x0010 729 #define PCIEM_TYPE_ROOT_PORT 0x0040 730 #define PCIEM_TYPE_UPSTREAM_PORT 0x0050 731 #define PCIEM_TYPE_DOWNSTREAM_PORT 0x0060 732 #define PCIEM_TYPE_PCI_BRIDGE 0x0070 733 #define PCIEM_TYPE_PCIE_BRIDGE 0x0080 734 #define PCIEM_TYPE_ROOT_INT_EP 0x0090 735 #define PCIEM_TYPE_ROOT_EC 0x00a0 736 #define PCIEM_FLAGS_SLOT 0x0100 737 #define PCIEM_FLAGS_IRQ 0x3e00 738 #define PCIER_DEVICE_CAP 0x4 739 #define PCIEM_CAP_MAX_PAYLOAD 0x00000007 740 #define PCIEM_CAP_PHANTHOM_FUNCS 0x00000018 741 #define PCIEM_CAP_EXT_TAG_FIELD 0x00000020 742 #define PCIEM_CAP_L0S_LATENCY 0x000001c0 743 #define PCIEM_CAP_L1_LATENCY 0x00000e00 744 #define PCIEM_CAP_ROLE_ERR_RPT 0x00008000 745 #define PCIEM_CAP_SLOT_PWR_LIM_VAL 0x03fc0000 746 #define PCIEM_CAP_SLOT_PWR_LIM_SCALE 0x0c000000 747 #define PCIEM_CAP_FLR 0x10000000 748 #define PCIER_DEVICE_CTL 0x8 749 #define PCIEM_CTL_COR_ENABLE 0x0001 750 #define PCIEM_CTL_NFER_ENABLE 0x0002 751 #define PCIEM_CTL_FER_ENABLE 0x0004 752 #define PCIEM_CTL_URR_ENABLE 0x0008 753 #define PCIEM_CTL_RELAXED_ORD_ENABLE 0x0010 754 #define PCIEM_CTL_MAX_PAYLOAD 0x00e0 755 #define PCIEM_CTL_EXT_TAG_FIELD 0x0100 756 #define PCIEM_CTL_PHANTHOM_FUNCS 0x0200 757 #define PCIEM_CTL_AUX_POWER_PM 0x0400 758 #define PCIEM_CTL_NOSNOOP_ENABLE 0x0800 759 #define PCIEM_CTL_MAX_READ_REQUEST 0x7000 760 #define PCIEM_CTL_BRDG_CFG_RETRY 0x8000 /* PCI-E - PCI/PCI-X bridges */ 761 #define PCIEM_CTL_INITIATE_FLR 0x8000 /* FLR capable endpoints */ 762 #define PCIER_DEVICE_STA 0xa 763 #define PCIEM_STA_CORRECTABLE_ERROR 0x0001 764 #define PCIEM_STA_NON_FATAL_ERROR 0x0002 765 #define PCIEM_STA_FATAL_ERROR 0x0004 766 #define PCIEM_STA_UNSUPPORTED_REQ 0x0008 767 #define PCIEM_STA_AUX_POWER 0x0010 768 #define PCIEM_STA_TRANSACTION_PND 0x0020 769 #define PCIER_LINK_CAP 0xc 770 #define PCIEM_LINK_CAP_MAX_SPEED 0x0000000f 771 #define PCIEM_LINK_CAP_MAX_WIDTH 0x000003f0 772 #define PCIEM_LINK_CAP_ASPM 0x00000c00 773 #define PCIEM_LINK_CAP_L0S_EXIT 0x00007000 774 #define PCIEM_LINK_CAP_L1_EXIT 0x00038000 775 #define PCIEM_LINK_CAP_CLOCK_PM 0x00040000 776 #define PCIEM_LINK_CAP_SURPRISE_DOWN 0x00080000 777 #define PCIEM_LINK_CAP_DL_ACTIVE 0x00100000 778 #define PCIEM_LINK_CAP_LINK_BW_NOTIFY 0x00200000 779 #define PCIEM_LINK_CAP_ASPM_COMPLIANCE 0x00400000 780 #define PCIEM_LINK_CAP_PORT 0xff000000 781 #define PCIER_LINK_CTL 0x10 782 #define PCIEM_LINK_CTL_ASPMC_DIS 0x0000 783 #define PCIEM_LINK_CTL_ASPMC_L0S 0x0001 784 #define PCIEM_LINK_CTL_ASPMC_L1 0x0002 785 #define PCIEM_LINK_CTL_ASPMC 0x0003 786 #define PCIEM_LINK_CTL_RCB 0x0008 787 #define PCIEM_LINK_CTL_LINK_DIS 0x0010 788 #define PCIEM_LINK_CTL_RETRAIN_LINK 0x0020 789 #define PCIEM_LINK_CTL_COMMON_CLOCK 0x0040 790 #define PCIEM_LINK_CTL_EXTENDED_SYNC 0x0080 791 #define PCIEM_LINK_CTL_ECPM 0x0100 792 #define PCIEM_LINK_CTL_HAWD 0x0200 793 #define PCIEM_LINK_CTL_LBMIE 0x0400 794 #define PCIEM_LINK_CTL_LABIE 0x0800 795 #define PCIER_LINK_STA 0x12 796 #define PCIEM_LINK_STA_SPEED 0x000f 797 #define PCIEM_LINK_STA_WIDTH 0x03f0 798 #define PCIEM_LINK_STA_TRAINING_ERROR 0x0400 799 #define PCIEM_LINK_STA_TRAINING 0x0800 800 #define PCIEM_LINK_STA_SLOT_CLOCK 0x1000 801 #define PCIEM_LINK_STA_DL_ACTIVE 0x2000 802 #define PCIEM_LINK_STA_LINK_BW_MGMT 0x4000 803 #define PCIEM_LINK_STA_LINK_AUTO_BW 0x8000 804 #define PCIER_SLOT_CAP 0x14 805 #define PCIEM_SLOT_CAP_APB 0x00000001 806 #define PCIEM_SLOT_CAP_PCP 0x00000002 807 #define PCIEM_SLOT_CAP_MRLSP 0x00000004 808 #define PCIEM_SLOT_CAP_AIP 0x00000008 809 #define PCIEM_SLOT_CAP_PIP 0x00000010 810 #define PCIEM_SLOT_CAP_HPS 0x00000020 811 #define PCIEM_SLOT_CAP_HPC 0x00000040 812 #define PCIEM_SLOT_CAP_SPLV 0x00007f80 813 #define PCIEM_SLOT_CAP_SPLS 0x00018000 814 #define PCIEM_SLOT_CAP_EIP 0x00020000 815 #define PCIEM_SLOT_CAP_NCCS 0x00040000 816 #define PCIEM_SLOT_CAP_PSN 0xfff80000 817 #define PCIER_SLOT_CTL 0x18 818 #define PCIEM_SLOT_CTL_ABPE 0x0001 819 #define PCIEM_SLOT_CTL_PFDE 0x0002 820 #define PCIEM_SLOT_CTL_MRLSCE 0x0004 821 #define PCIEM_SLOT_CTL_PDCE 0x0008 822 #define PCIEM_SLOT_CTL_CCIE 0x0010 823 #define PCIEM_SLOT_CTL_HPIE 0x0020 824 #define PCIEM_SLOT_CTL_AIC 0x00c0 825 #define PCIEM_SLOT_CTL_AI_ON 0x0040 826 #define PCIEM_SLOT_CTL_AI_BLINK 0x0080 827 #define PCIEM_SLOT_CTL_AI_OFF 0x00c0 828 #define PCIEM_SLOT_CTL_PIC 0x0300 829 #define PCIEM_SLOT_CTL_PI_ON 0x0100 830 #define PCIEM_SLOT_CTL_PI_BLINK 0x0200 831 #define PCIEM_SLOT_CTL_PI_OFF 0x0300 832 #define PCIEM_SLOT_CTL_PCC 0x0400 833 #define PCIEM_SLOT_CTL_PC_ON 0x0000 834 #define PCIEM_SLOT_CTL_PC_OFF 0x0400 835 #define PCIEM_SLOT_CTL_EIC 0x0800 836 #define PCIEM_SLOT_CTL_DLLSCE 0x1000 837 #define PCIER_SLOT_STA 0x1a 838 #define PCIEM_SLOT_STA_ABP 0x0001 839 #define PCIEM_SLOT_STA_PFD 0x0002 840 #define PCIEM_SLOT_STA_MRLSC 0x0004 841 #define PCIEM_SLOT_STA_PDC 0x0008 842 #define PCIEM_SLOT_STA_CC 0x0010 843 #define PCIEM_SLOT_STA_MRLSS 0x0020 844 #define PCIEM_SLOT_STA_PDS 0x0040 845 #define PCIEM_SLOT_STA_EIS 0x0080 846 #define PCIEM_SLOT_STA_DLLSC 0x0100 847 #define PCIER_ROOT_CTL 0x1c 848 #define PCIEM_ROOT_CTL_SERR_CORR 0x0001 849 #define PCIEM_ROOT_CTL_SERR_NONFATAL 0x0002 850 #define PCIEM_ROOT_CTL_SERR_FATAL 0x0004 851 #define PCIEM_ROOT_CTL_PME 0x0008 852 #define PCIEM_ROOT_CTL_CRS_VIS 0x0010 853 #define PCIER_ROOT_CAP 0x1e 854 #define PCIEM_ROOT_CAP_CRS_VIS 0x0001 855 #define PCIER_ROOT_STA 0x20 856 #define PCIEM_ROOT_STA_PME_REQID_MASK 0x0000ffff 857 #define PCIEM_ROOT_STA_PME_STATUS 0x00010000 858 #define PCIEM_ROOT_STA_PME_PEND 0x00020000 859 #define PCIER_DEVICE_CAP2 0x24 860 #define PCIEM_CAP2_COMP_TIMO_RANGES 0x0000000f 861 #define PCIEM_CAP2_COMP_TIMO_RANGE_A 0x00000001 862 #define PCIEM_CAP2_COMP_TIMO_RANGE_B 0x00000002 863 #define PCIEM_CAP2_COMP_TIMO_RANGE_C 0x00000004 864 #define PCIEM_CAP2_COMP_TIMO_RANGE_D 0x00000008 865 #define PCIEM_CAP2_COMP_TIMO_DISABLE 0x00000010 866 #define PCIEM_CAP2_ARI 0x00000020 867 #define PCIER_DEVICE_CTL2 0x28 868 #define PCIEM_CTL2_COMP_TIMO_VAL 0x000f 869 #define PCIEM_CTL2_COMP_TIMO_50MS 0x0000 870 #define PCIEM_CTL2_COMP_TIMO_100US 0x0001 871 #define PCIEM_CTL2_COMP_TIMO_10MS 0x0002 872 #define PCIEM_CTL2_COMP_TIMO_55MS 0x0005 873 #define PCIEM_CTL2_COMP_TIMO_210MS 0x0006 874 #define PCIEM_CTL2_COMP_TIMO_900MS 0x0009 875 #define PCIEM_CTL2_COMP_TIMO_3500MS 0x000a 876 #define PCIEM_CTL2_COMP_TIMO_13S 0x000d 877 #define PCIEM_CTL2_COMP_TIMO_64S 0x000e 878 #define PCIEM_CTL2_COMP_TIMO_DISABLE 0x0010 879 #define PCIEM_CTL2_ARI 0x0020 880 #define PCIEM_CTL2_ATOMIC_REQ_ENABLE 0x0040 881 #define PCIEM_CTL2_ATOMIC_EGR_BLOCK 0x0080 882 #define PCIEM_CTL2_ID_ORDERED_REQ_EN 0x0100 883 #define PCIEM_CTL2_ID_ORDERED_CMP_EN 0x0200 884 #define PCIEM_CTL2_LTR_ENABLE 0x0400 885 #define PCIEM_CTL2_OBFF 0x6000 886 #define PCIEM_OBFF_DISABLE 0x0000 887 #define PCIEM_OBFF_MSGA_ENABLE 0x2000 888 #define PCIEM_OBFF_MSGB_ENABLE 0x4000 889 #define PCIEM_OBFF_WAKE_ENABLE 0x6000 890 #define PCIEM_CTL2_END2END_TLP 0x8000 891 #define PCIER_DEVICE_STA2 0x2a 892 #define PCIER_LINK_CAP2 0x2c 893 #define PCIER_LINK_CTL2 0x30 894 #define PCIEM_LNKCTL2_TLS 0x000f 895 #define PCIEM_LNKCTL2_TLS_2_5GT 0x0001 896 #define PCIEM_LNKCTL2_TLS_5_0GT 0x0002 897 #define PCIEM_LNKCTL2_TLS_8_0GT 0x0003 898 #define PCIEM_LNKCTL2_TLS_16_0GT 0x0004 899 #define PCIEM_LNKCTL2_TLS_32_0GT 0x0005 900 #define PCIEM_LNKCTL2_TLS_64_0GT 0x0006 901 #define PCIEM_LNKCTL2_ENTER_COMP 0x0010 902 #define PCIEM_LNKCTL2_TX_MARGIN 0x0380 903 #define PCIEM_LNKCTL2_HASD 0x0020 904 #define PCIER_LINK_STA2 0x32 905 #define PCIER_SLOT_CAP2 0x34 906 #define PCIER_SLOT_CTL2 0x38 907 #define PCIER_SLOT_STA2 0x3a 908 909 /* MSI-X definitions */ 910 #define PCIR_MSIX_CTRL 0x2 911 #define PCIM_MSIXCTRL_MSIX_ENABLE 0x8000 912 #define PCIM_MSIXCTRL_FUNCTION_MASK 0x4000 913 #define PCIM_MSIXCTRL_TABLE_SIZE 0x07ff 914 #define PCIR_MSIX_TABLE 0x4 915 #define PCIR_MSIX_PBA 0x8 916 #define PCIM_MSIX_BIR_MASK 0x7 917 #define PCIM_MSIX_TABLE_OFFSET 0xfffffff8 918 #define PCIM_MSIX_BIR_BAR_10 0 919 #define PCIM_MSIX_BIR_BAR_14 1 920 #define PCIM_MSIX_BIR_BAR_18 2 921 #define PCIM_MSIX_BIR_BAR_1C 3 922 #define PCIM_MSIX_BIR_BAR_20 4 923 #define PCIM_MSIX_BIR_BAR_24 5 924 #define PCIM_MSIX_ENTRY_SIZE 16 925 #define PCIM_MSIX_ENTRY_LOWER_ADDR 0x0 /* Message Address */ 926 #define PCIM_MSIX_ENTRY_UPPER_ADDR 0x4 /* Message Upper Address */ 927 #define PCIM_MSIX_ENTRY_DATA 0x8 /* Message Data */ 928 #define PCIM_MSIX_ENTRY_VECTOR_CTRL 0xc /* Vector Control */ 929 #define PCIM_MSIX_ENTRYVECTOR_CTRL_MASK 0x1 930 931 /* PCI Advanced Features definitions */ 932 #define PCIR_PCIAF_CAP 0x3 933 #define PCIM_PCIAFCAP_TP 0x01 934 #define PCIM_PCIAFCAP_FLR 0x02 935 #define PCIR_PCIAF_CTRL 0x4 936 #define PCIR_PCIAFCTRL_FLR 0x01 937 #define PCIR_PCIAF_STATUS 0x5 938 #define PCIR_PCIAFSTATUS_TP 0x01 939 940 /* Advanced Error Reporting */ 941 #define PCIR_AER_UC_STATUS 0x04 942 #define PCIM_AER_UC_TRAINING_ERROR 0x00000001 943 #define PCIM_AER_UC_DL_PROTOCOL_ERROR 0x00000010 944 #define PCIM_AER_UC_SURPRISE_LINK_DOWN 0x00000020 945 #define PCIM_AER_UC_POISONED_TLP 0x00001000 946 #define PCIM_AER_UC_FC_PROTOCOL_ERROR 0x00002000 947 #define PCIM_AER_UC_COMPLETION_TIMEOUT 0x00004000 948 #define PCIM_AER_UC_COMPLETER_ABORT 0x00008000 949 #define PCIM_AER_UC_UNEXPECTED_COMPLETION 0x00010000 950 #define PCIM_AER_UC_RECEIVER_OVERFLOW 0x00020000 951 #define PCIM_AER_UC_MALFORMED_TLP 0x00040000 952 #define PCIM_AER_UC_ECRC_ERROR 0x00080000 953 #define PCIM_AER_UC_UNSUPPORTED_REQUEST 0x00100000 954 #define PCIM_AER_UC_ACS_VIOLATION 0x00200000 955 #define PCIM_AER_UC_INTERNAL_ERROR 0x00400000 956 #define PCIM_AER_UC_MC_BLOCKED_TLP 0x00800000 957 #define PCIM_AER_UC_ATOMIC_EGRESS_BLK 0x01000000 958 #define PCIM_AER_UC_TLP_PREFIX_BLOCKED 0x02000000 959 #define PCIR_AER_UC_MASK 0x08 /* Shares bits with UC_STATUS */ 960 #define PCIR_AER_UC_SEVERITY 0x0c /* Shares bits with UC_STATUS */ 961 #define PCIR_AER_COR_STATUS 0x10 962 #define PCIM_AER_COR_RECEIVER_ERROR 0x00000001 963 #define PCIM_AER_COR_BAD_TLP 0x00000040 964 #define PCIM_AER_COR_BAD_DLLP 0x00000080 965 #define PCIM_AER_COR_REPLAY_ROLLOVER 0x00000100 966 #define PCIM_AER_COR_REPLAY_TIMEOUT 0x00001000 967 #define PCIM_AER_COR_ADVISORY_NF_ERROR 0x00002000 968 #define PCIM_AER_COR_INTERNAL_ERROR 0x00004000 969 #define PCIM_AER_COR_HEADER_LOG_OVFLOW 0x00008000 970 #define PCIR_AER_COR_MASK 0x14 /* Shares bits with COR_STATUS */ 971 #define PCIR_AER_CAP_CONTROL 0x18 972 #define PCIM_AER_FIRST_ERROR_PTR 0x0000001f 973 #define PCIM_AER_ECRC_GEN_CAPABLE 0x00000020 974 #define PCIM_AER_ECRC_GEN_ENABLE 0x00000040 975 #define PCIM_AER_ECRC_CHECK_CAPABLE 0x00000080 976 #define PCIM_AER_ECRC_CHECK_ENABLE 0x00000100 977 #define PCIM_AER_MULT_HDR_CAPABLE 0x00000200 978 #define PCIM_AER_MULT_HDR_ENABLE 0x00000400 979 #define PCIM_AER_TLP_PREFIX_LOG_PRESENT 0x00000800 980 #define PCIR_AER_HEADER_LOG 0x1c 981 #define PCIR_AER_ROOTERR_CMD 0x2c /* Only for root complex ports */ 982 #define PCIM_AER_ROOTERR_COR_ENABLE 0x00000001 983 #define PCIM_AER_ROOTERR_NF_ENABLE 0x00000002 984 #define PCIM_AER_ROOTERR_F_ENABLE 0x00000004 985 #define PCIR_AER_ROOTERR_STATUS 0x30 /* Only for root complex ports */ 986 #define PCIM_AER_ROOTERR_COR_ERR 0x00000001 987 #define PCIM_AER_ROOTERR_MULTI_COR_ERR 0x00000002 988 #define PCIM_AER_ROOTERR_UC_ERR 0x00000004 989 #define PCIM_AER_ROOTERR_MULTI_UC_ERR 0x00000008 990 #define PCIM_AER_ROOTERR_FIRST_UC_FATAL 0x00000010 991 #define PCIM_AER_ROOTERR_NF_ERR 0x00000020 992 #define PCIM_AER_ROOTERR_F_ERR 0x00000040 993 #define PCIM_AER_ROOTERR_INT_MESSAGE 0xf8000000 994 #define PCIR_AER_COR_SOURCE_ID 0x34 /* Only for root complex ports */ 995 #define PCIR_AER_ERR_SOURCE_ID 0x36 /* Only for root complex ports */ 996 #define PCIR_AER_TLP_PREFIX_LOG 0x38 /* Only for TLP prefix functions */ 997 998 /* Virtual Channel definitions */ 999 #define PCIR_VC_CAP1 0x04 1000 #define PCIM_VC_CAP1_EXT_COUNT 0x00000007 1001 #define PCIM_VC_CAP1_LOWPRI_EXT_COUNT 0x00000070 1002 #define PCIR_VC_CAP2 0x08 1003 #define PCIR_VC_CONTROL 0x0c 1004 #define PCIR_VC_STATUS 0x0e 1005 #define PCIR_VC_RESOURCE_CAP(n) (0x10 + (n) * 0x0c) 1006 #define PCIR_VC_RESOURCE_CTL(n) (0x14 + (n) * 0x0c) 1007 #define PCIR_VC_RESOURCE_STA(n) (0x18 + (n) * 0x0c) 1008 1009 /* Serial Number definitions */ 1010 #define PCIR_SERIAL_LOW 0x04 1011 #define PCIR_SERIAL_HIGH 0x08 1012 1013 /* SR-IOV definitions */ 1014 #define PCIR_SRIOV_CTL 0x08 1015 #define PCIM_SRIOV_VF_EN 0x01 1016 #define PCIM_SRIOV_VF_MSE 0x08 /* Memory space enable. */ 1017 #define PCIM_SRIOV_ARI_EN 0x10 1018 #define PCIR_SRIOV_TOTAL_VFS 0x0e 1019 #define PCIR_SRIOV_NUM_VFS 0x10 1020 #define PCIR_SRIOV_VF_OFF 0x14 1021 #define PCIR_SRIOV_VF_STRIDE 0x16 1022 #define PCIR_SRIOV_VF_DID 0x1a 1023 #define PCIR_SRIOV_PAGE_CAP 0x1c 1024 #define PCIR_SRIOV_PAGE_SIZE 0x20 1025 1026 #define PCI_SRIOV_BASE_PAGE_SHIFT 12 1027 1028 #define PCIR_SRIOV_BARS 0x24 1029 #define PCIR_SRIOV_BAR(x) (PCIR_SRIOV_BARS + (x) * 4) 1030 1031 /* Extended Capability Vendor-Specific definitions */ 1032 #define PCIR_VSEC_HEADER 0x04 1033 #define PCIR_VSEC_ID(hdr) ((hdr) & 0xffff) 1034 #define PCIR_VSEC_REV(hdr) (((hdr) & 0xf0000) >> 16) 1035 #define PCIR_VSEC_LENGTH(hdr) (((hdr) & 0xfff00000) >> 20) 1036 #define PCIR_VSEC_DATA 0x08 1037 1038 /* ASPM L1 PM Substates */ 1039 #define PCIR_L1SS_CAP 0x04 /* Capabilities Register */ 1040 #define PCIM_L1SS_CAP_PCIPM_L1_2 0x00000001 /* PCI-PM L1.2 Supported */ 1041 #define PCIM_L1SS_CAP_PCIPM_L1_1 0x00000002 /* PCI-PM L1.1 Supported */ 1042 #define PCIM_L1SS_CAP_ASPM_L1_2 0x00000004 /* ASPM L1.2 Supported */ 1043 #define PCIM_L1SS_CAP_ASPM_L1_1 0x00000008 /* ASPM L1.1 Supported */ 1044 #define PCIM_L1SS_CAP_L1_PM_SS 0x00000010 /* L1 PM Substates Supported */ 1045 #define PCIM_L1SS_CAP_CM_RESTORE_TIME 0x0000ff00 /* Port Common_Mode_Restore_Time */ 1046 #define PCIM_L1SS_CAP_P_PWR_ON_SCALE 0x00030000 /* Port T_POWER_ON scale */ 1047 #define PCIM_L1SS_CAP_P_PWR_ON_VALUE 0x00f80000 /* Port T_POWER_ON value */ 1048 #define PCIR_L1SS_CTL1 0x08 /* Control 1 Register */ 1049 #define PCIM_L1SS_CTL1_PCIPM_L1_2 0x00000001 /* PCI-PM L1.2 Enable */ 1050 #define PCIM_L1SS_CTL1_PCIPM_L1_1 0x00000002 /* PCI-PM L1.1 Enable */ 1051 #define PCIM_L1SS_CTL1_ASPM_L1_2 0x00000004 /* ASPM L1.2 Enable */ 1052 #define PCIM_L1SS_CTL1_ASPM_L1_1 0x00000008 /* ASPM L1.1 Enable */ 1053 #define PCIM_L1SS_CTL1_L1_2_MASK 0x00000005 1054 #define PCIM_L1SS_CTL1_L1SS_MASK 0x0000000f 1055 #define PCIM_L1SS_CTL1_CM_RESTORE_TIME 0x0000ff00 /* Common_Mode_Restore_Time */ 1056 #define PCIM_L1SS_CTL1_LTR_L12_TH_VALUE 0x03ff0000 /* LTR_L1.2_THRESHOLD_Value */ 1057 #define PCIM_L1SS_CTL1_LTR_L12_TH_SCALE 0xe0000000 /* LTR_L1.2_THRESHOLD_Scale */ 1058 #define PCIR_L1SS_CTL2 0x0c /* Control 2 Register */ 1059 #define PCIM_L1SS_CTL2_T_PWR_ON_SCALE 0x00000003 /* T_POWER_ON Scale */ 1060 #define PCIM_L1SS_CTL2_T_PWR_ON_VALUE 0x000000f8 /* T_POWER_ON Value */ 1061 1062 /* Alternative Routing-ID Interpretation */ 1063 #define PCIR_ARI_CAP 0x04 /* Capabilities Register */ 1064 #define PCIM_ARI_CAP_MFVC 0x0001 /* MFVC Function Groups Capability */ 1065 #define PCIM_ARI_CAP_ACS 0x0002 /* ACS Function Groups Capability */ 1066 #define PCIM_ARI_CAP_NFN(x) (((x) >> 8) & 0xff) /* Next Function Number */ 1067 #define PCIR_ARI_CTRL 0x06 /* ARI Control Register */ 1068 #define PCIM_ARI_CTRL_MFVC 0x0001 /* MFVC Function Groups Enable */ 1069 #define PCIM_ARI_CTRL_ACS 0x0002 /* ACS Function Groups Enable */ 1070 #define PCIM_ARI_CTRL_FG(x) (((x) >> 4) & 7) /* Function Group */ 1071 #define PCIR_EXT_CAP_ARI_SIZEOF 8 1072 1073 /* 1074 * PCI Express Firmware Interface definitions 1075 */ 1076 #define PCI_OSC_STATUS 0 1077 #define PCI_OSC_SUPPORT 1 1078 #define PCIM_OSC_SUPPORT_EXT_PCI_CONF 0x01 /* Extended PCI Config Space */ 1079 #define PCIM_OSC_SUPPORT_ASPM 0x02 /* Active State Power Management */ 1080 #define PCIM_OSC_SUPPORT_CPMC 0x04 /* Clock Power Management Cap */ 1081 #define PCIM_OSC_SUPPORT_SEG_GROUP 0x08 /* PCI Segment Groups supported */ 1082 #define PCIM_OSC_SUPPORT_MSI 0x10 /* MSI signalling supported */ 1083 #define PCI_OSC_CTL 2 1084 #define PCIM_OSC_CTL_PCIE_HP 0x01 /* PCIe Native Hot Plug */ 1085 #define PCIM_OSC_CTL_SHPC_HP 0x02 /* SHPC Native Hot Plug */ 1086 #define PCIM_OSC_CTL_PCIE_PME 0x04 /* PCIe Native Power Mgt Events */ 1087 #define PCIM_OSC_CTL_PCIE_AER 0x08 /* PCIe Advanced Error Reporting */ 1088 #define PCIM_OSC_CTL_PCIE_CAP_STRUCT 0x10 /* Various Capability Structures */ 1089 1090 #endif /* __PCI_REGS_H__ */ 1091