PORT_LOGIC_LINK_WIDTH_1_LANES (reference) in projects: components

Searched refs:PORT_LOGIC_LINK_WIDTH_1_LANES (Results 1 – 2 of 2) sorted by relevance

/components/drivers/pci/host/dw/
A D	pcie-dw.h	`61 #define PORT_LOGIC_LINK_WIDTH_1_LANES PORT_LOGIC_LINK_WIDTH(0x1) macro`
A D	pcie-dw.c	`638 case 1: val \|= PORT_LOGIC_LINK_WIDTH_1_LANES; break; in dw_pcie_setup()`

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