1 /*
2 * Copyright (c) 2024, sakumisu
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6 #include "sys_driver.h"
7 #include "gpio_driver.h"
8 #include <driver/gpio.h>
9 #include <driver/gpio_types.h>
10 #include <driver/int.h>
11 #include "bk_misc.h"
12 #include "usbd_core.h"
13 #include "usbh_core.h"
14 #include "usb_musb_reg.h"
15
16 #define USB_BASE_ADDR SOC_USB_REG_BASE
17
18 #if (CONFIG_SOC_BK7271)
19 #define REG_AHB2_USB_OTG_CFG (*((volatile unsigned char *)(USB_BASE_ADDR + 0x80)))
20 #define REG_AHB2_USB_DMA_ENDP (*((volatile unsigned char *)(USB_BASE_ADDR + 0x84)))
21 #define REG_AHB2_USB_VTH (*((volatile unsigned char *)(USB_BASE_ADDR + 0x88)))
22 #define REG_AHB2_USB_GEN (*((volatile unsigned char *)(USB_BASE_ADDR + 0x8C)))
23 #define REG_AHB2_USB_STAT (*((volatile unsigned char *)(USB_BASE_ADDR + 0x90)))
24 #define REG_AHB2_USB_INT (*((volatile unsigned char *)(USB_BASE_ADDR + 0x94)))
25 #define REG_AHB2_USB_RESET (*((volatile unsigned char *)(USB_BASE_ADDR + 0x98)))
26 #define REG_AHB2_USB_DEV_CFG (*((volatile unsigned char *)(USB_BASE_ADDR + 0x9C)))
27 #elif (CONFIG_SOC_BK7256XX)
28 #define REG_AHB2_USB_OTG_CFG (*((volatile unsigned char *)(USB_BASE_ADDR + 0x280)))
29 #define REG_AHB2_USB_DMA_ENDP (*((volatile unsigned char *)(USB_BASE_ADDR + 0x284)))
30 #define REG_AHB2_USB_VTH (*((volatile unsigned char *)(USB_BASE_ADDR + 0x288)))
31 #define REG_AHB2_USB_GEN (*((volatile unsigned char *)(USB_BASE_ADDR + 0x28C)))
32 #define REG_AHB2_USB_STAT (*((volatile unsigned char *)(USB_BASE_ADDR + 0x290)))
33 #define REG_AHB2_USB_INT (*((volatile unsigned char *)(USB_BASE_ADDR + 0x294)))
34 #define REG_AHB2_USB_RESET (*((volatile unsigned char *)(USB_BASE_ADDR + 0x298)))
35 #define REG_AHB2_USB_DEV_CFG (*((volatile unsigned char *)(USB_BASE_ADDR + 0x29C)))
36 #elif (CONFIG_SOC_BK7236XX) || (CONFIG_SOC_BK7239XX) || (CONFIG_SOC_BK7286XX)
37 #define REG_AHB2_USB_DEVICE_ID (*((volatile unsigned char *)(USB_BASE_ADDR + 0x280)))
38 #define REG_AHB2_USB_VERSION_ID (*((volatile unsigned char *)(USB_BASE_ADDR + 0x284)))
39 #define REG_AHB2_USB_GLOBAL_CTRL (*((volatile unsigned char *)(USB_BASE_ADDR + 0x288)))
40 #define REG_AHB2_USB_DEVICE_STATUS (*((volatile unsigned char *)(USB_BASE_ADDR + 0x28c)))
41 #define REG_AHB2_USB_OTG_CFG (*((volatile unsigned char *)(USB_BASE_ADDR + 0x290)))
42 #define REG_AHB2_USB_DMA_ENDP (*((volatile unsigned char *)(USB_BASE_ADDR + 0x294)))
43 #define REG_AHB2_USB_VTH (*((volatile unsigned char *)(USB_BASE_ADDR + 0x298)))
44 #define REG_AHB2_USB_GEN (*((volatile unsigned char *)(USB_BASE_ADDR + 0x29C)))
45 #define REG_AHB2_USB_STAT (*((volatile unsigned char *)(USB_BASE_ADDR + 0x2A0)))
46 #define REG_AHB2_USB_INT (*((volatile unsigned char *)(USB_BASE_ADDR + 0x2A4)))
47 #define REG_AHB2_USB_RESET (*((volatile unsigned char *)(USB_BASE_ADDR + 0x2A8)))
48 #define REG_AHB2_USB_DEV_CFG (*((volatile unsigned char *)(USB_BASE_ADDR + 0x2AC)))
49
50 #define REG_USB_USR_700 (*((volatile unsigned long *)(USB_BASE_ADDR + 0x700)))
51 #define REG_USB_USR_704 (*((volatile unsigned long *)(USB_BASE_ADDR + 0x704)))
52 #define REG_USB_USR_708 (*((volatile unsigned long *)(USB_BASE_ADDR + 0x708)))
53 #define REG_USB_USR_70C (*((volatile unsigned long *)(USB_BASE_ADDR + 0x70C)))
54 #define REG_USB_USR_710 (*((volatile unsigned long *)(USB_BASE_ADDR + 0x710)))
55 #define REG_USB_USR_714 (*((volatile unsigned long *)(USB_BASE_ADDR + 0x714)))
56 #define REG_USB_PHY_00 (*((volatile unsigned long *)(USB_BASE_ADDR + 0x400)))
57 #define REG_USB_PHY_01 (*((volatile unsigned long *)(USB_BASE_ADDR + 0x404)))
58 #endif
59
60 #define USB_DP_CAPABILITY_VALUE (0xF)
61 #define USB_DN_CAPABILITY_VALUE (0xF)
62
63 #define NANENG_PHY_FC_REG01 (0x01 * 4)
64 #define NANENG_PHY_FC_REG02 (0x02 * 4)
65 #define NANENG_PHY_FC_REG03 (0x03 * 4)
66 #define NANENG_PHY_FC_REG04 (0x04 * 4)
67 #define NANENG_PHY_FC_REG05 (0x05 * 4)
68 #define NANENG_PHY_FC_REG06 (0x06 * 4)
69 #define NANENG_PHY_FC_REG07 (0x07 * 4)
70 #define NANENG_PHY_FC_REG08 (0x08 * 4)
71 #define NANENG_PHY_FC_REG09 (0x09 * 4)
72 #define NANENG_PHY_FC_REG0A (0x0A * 4)
73 #define NANENG_PHY_FC_REG0B (0x0B * 4)
74 #define NANENG_PHY_FC_REG0C (0x0C * 4)
75 #define NANENG_PHY_FC_REG0D (0x0D * 4)
76 #define NANENG_PHY_FC_REG0E (0x0E * 4)
77 #define NANENG_PHY_FC_REG0F (0x0F * 4)
78 #define NANENG_PHY_FC_REG0F_BYTE 0x0F
79
80 #define NANENG_PHY_FC_REG10 (0x10 * 4)
81 #define NANENG_PHY_FC_REG11 (0x11 * 4)
82 #define NANENG_PHY_FC_REG12 (0x12 * 4)
83 #define NANENG_PHY_FC_REG13 (0x13 * 4)
84 #define NANENG_PHY_FC_REG14 (0x14 * 4)
85 #define NANENG_PHY_FC_REG15 (0x15 * 4)
86 #define NANENG_PHY_FC_REG16 (0x16 * 4)
87 #define NANENG_PHY_FC_REG17 (0x17 * 4)
88 #define NANENG_PHY_FC_REG18 (0x18 * 4)
89 #define NANENG_PHY_FC_REG19 (0x19 * 4)
90 #define NANENG_PHY_FC_REG1A (0x1A * 4)
91 #define NANENG_PHY_FC_REG1B (0x1B * 4)
92 #define NANENG_PHY_FC_REG1C (0x1C * 4)
93 #define NANENG_PHY_FC_REG1D (0x1D * 4)
94 #define NANENG_PHY_FC_REG1E (0x1E * 4)
95 #define NANENG_PHY_FC_REG1F (0x1F * 4)
96
97 #if CONFIG_USB_MUSB_EP_NUM != 8
98 #error beken chips only support 8 endpoints
99 #endif
100
101 #if CONFIG_USB_MUSB_PIPE_NUM != 8
102 #error beken chips only support 8 pipes
103 #endif
104
105 // clang-format off
106 static struct musb_fifo_cfg musb_device_table[] = {
107 { .ep_num = 0, .style = FIFO_TXRX, .maxpacket = 64, },
108 { .ep_num = 1, .style = FIFO_TX, .maxpacket = 1024, },
109 { .ep_num = 1, .style = FIFO_RX, .maxpacket = 1024, },
110 { .ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
111 { .ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
112 { .ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
113 { .ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
114 { .ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
115 { .ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
116 { .ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
117 { .ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
118 { .ep_num = 6, .style = FIFO_TXRX, .maxpacket = 512, },
119 { .ep_num = 7, .style = FIFO_TXRX, .maxpacket = 512, }
120 };
121
122 static struct musb_fifo_cfg musb_host_table[] = {
123 { .ep_num = 0, .style = FIFO_TXRX, .maxpacket = 64, },
124 { .ep_num = 1, .style = FIFO_TX, .maxpacket = 1024, },
125 { .ep_num = 1, .style = FIFO_RX, .maxpacket = 1024, },
126 { .ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
127 { .ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
128 { .ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
129 { .ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
130 { .ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
131 { .ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
132 { .ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
133 { .ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
134 { .ep_num = 6, .style = FIFO_TXRX, .maxpacket = 512, },
135 { .ep_num = 7, .style = FIFO_TXRX, .maxpacket = 512, }
136 };
137 // clang-format on
138
usbd_get_musb_fifo_cfg(struct musb_fifo_cfg ** cfg)139 uint8_t usbd_get_musb_fifo_cfg(struct musb_fifo_cfg **cfg)
140 {
141 *cfg = musb_device_table;
142 return sizeof(musb_device_table) / sizeof(musb_device_table[0]);
143 }
144
usbh_get_musb_fifo_cfg(struct musb_fifo_cfg ** cfg)145 uint8_t usbh_get_musb_fifo_cfg(struct musb_fifo_cfg **cfg)
146 {
147 *cfg = musb_host_table;
148 return sizeof(musb_host_table) / sizeof(musb_host_table[0]);
149 }
150
usb_get_musb_ram_size(void)151 uint32_t usb_get_musb_ram_size(void)
152 {
153 return 8192;
154 }
155
156 extern void USBD_IRQHandler(uint8_t busid);
157
USBD_IRQ(void)158 void USBD_IRQ(void)
159 {
160 USBD_IRQHandler(0);
161 }
162
bk_analog_layer_usb_sys_related_ops(uint32_t usb_mode,bool ops)163 static void bk_analog_layer_usb_sys_related_ops(uint32_t usb_mode, bool ops)
164 {
165 extern void delay(INT32 num);
166
167 #if 0
168 sys_drv_usb_analog_phy_en(ops, NULL);
169 sys_drv_usb_analog_speed_en(ops, NULL);
170 sys_drv_usb_analog_ckmcu_en(ops, NULL);
171 #endif
172 if (ops) {
173 sys_drv_usb_clock_ctrl(true, NULL);
174 delay(100);
175 #if 0
176 sys_drv_usb_analog_deepsleep_en(false);
177 #endif
178 sys_drv_usb_analog_dp_capability(USB_DP_CAPABILITY_VALUE);
179 sys_drv_usb_analog_dn_capability(USB_DN_CAPABILITY_VALUE);
180 if (!sys_hal_psram_ldo_status()) {
181 sys_drv_psram_ldo_enable(1);
182 }
183 sys_drv_usb_analog_phy_en(1, NULL);
184
185 if (usb_mode == 0) {
186 REG_USB_USR_708 = 0x0;
187 REG_USB_USR_710 &= ~(0x1 << 7);
188 delay(100);
189
190 REG_USB_USR_710 |= (0x1 << 15);
191 //REG_USB_USR_710 |= (0x1<<14);
192 REG_USB_USR_710 |= (0x1 << 16);
193 REG_USB_USR_710 |= (0x1 << 17);
194 REG_USB_USR_710 |= (0x1 << 18);
195 REG_USB_USR_710 |= (0x1 << 19);
196 REG_USB_USR_710 &= ~(0x1 << 20);
197 REG_USB_USR_710 |= (0x1 << 21);
198 REG_USB_USR_710 |= (0x0 << 0);
199 REG_USB_USR_710 |= (0x1 << 5);
200 REG_USB_USR_710 |= (0x1 << 6);
201 REG_USB_USR_710 |= (0x1 << 9);
202 REG_USB_USR_710 |= (0x1 << 10);
203 REG_USB_USR_710 |= (0x1 << 1);
204
205 REG_USB_USR_710 |= (0x1 << 7);
206 REG_USB_USR_708 = 0x1;
207 #if 0
208 REG_USB_PHY_00 = 0x08;
209 REG_USB_PHY_01 = 0x02;
210 REG_USB_USR_710 |= (0x1<< 8);
211 while(1){
212 reg = REG_USB_USR_70C;
213 if(reg & 0x100){
214 USB_DRIVER_LOGI("SelfTest Fin!\r\n");
215 USB_DRIVER_LOGI("test end!\r\n");
216 break;
217 } else {
218 USB_DRIVER_LOGI("70c_reg:0x%x\r\n", reg);
219 delay(10000);
220 }
221 }
222 REG_USB_PHY_00 &= ~0x08;
223 REG_USB_PHY_01 &= ~0x02;
224 REG_USB_USR_710 &= ~(0x1<< 8);
225 #endif
226 } else {
227 REG_USB_USR_710 |= (0x1 << 15);
228 REG_USB_USR_710 |= (0x1 << 14);
229 REG_USB_USR_710 |= (0x1 << 16);
230 REG_USB_USR_710 |= (0x1 << 17);
231 REG_USB_USR_710 |= (0x1 << 18);
232 REG_USB_USR_710 |= (0x1 << 19);
233 REG_USB_USR_710 &= ~(0x1 << 20);
234 REG_USB_USR_710 |= (0x1 << 21);
235 REG_USB_USR_710 |= (0x0 << 0);
236 REG_USB_USR_710 |= (0x1 << 5);
237 REG_USB_USR_710 |= (0x1 << 6);
238 REG_USB_USR_710 |= (0x1 << 9);
239 REG_USB_USR_710 |= (0x1 << 10);
240 REG_USB_USR_710 |= (0x1 << 7);
241
242 REG_USB_USR_708 = 0x1;
243 }
244 } else {
245 sys_drv_usb_analog_phy_en(0, NULL);
246 sys_drv_usb_clock_ctrl(false, NULL);
247 }
248 }
249
usb_dc_low_level_init(void)250 void usb_dc_low_level_init(void)
251 {
252 #if CONFIG_SYS_CPU0
253 bk_pm_module_vote_sleep_ctrl(PM_SLEEP_MODULE_NAME_USB_1, 0x0, 0x0);
254 #endif
255 bk_analog_layer_usb_sys_related_ops(1, true);
256 bk_gpio_set_output_high(CONFIG_USB_VBAT_CONTROL_GPIO_ID);
257
258 bk_pm_module_vote_cpu_freq(PM_DEV_ID_USB_1, PM_CPU_FRQ_120M);
259
260 sys_hal_usb_analog_phy_en(true);
261
262 sys_drv_usb_clock_ctrl(true, NULL);
263 sys_drv_int_enable(USB_INTERRUPT_CTRL_BIT);
264
265 bk_int_isr_register(INT_SRC_USB, USBD_IRQ, NULL);
266 bk_int_set_priority(INT_SRC_USB, 2);
267 }
268
usb_dc_low_level_deinit(void)269 void usb_dc_low_level_deinit(void)
270 {
271 bk_pm_module_vote_cpu_freq(PM_DEV_ID_USB_1, PM_CPU_FRQ_DEFAULT);
272 sys_hal_usb_analog_phy_en(false);
273 sys_drv_usb_clock_ctrl(false, NULL);
274 sys_drv_int_disable(USB_INTERRUPT_CTRL_BIT);
275 bk_int_isr_unregister(INT_SRC_USB);
276 bk_analog_layer_usb_sys_related_ops(1, false);
277 sys_drv_dev_clk_pwr_up(CLK_PWR_ID_USB_1, CLK_PWR_CTRL_PWR_DOWN);
278 }
279
usbd_musb_delay_ms(uint8_t ms)280 void usbd_musb_delay_ms(uint8_t ms)
281 {
282 /* implement later */
283 }
284
285 extern void USBH_IRQHandler(uint8_t busid);
286
USBH_IRQ(void)287 void USBH_IRQ(void)
288 {
289 USBH_IRQHandler(0);
290 }
291
292 #define NANENG_PHY_CFG 1
293 #define USB_PHY_BASE (SOC_USB_REG_BASE + 0x400)
294
295 #define HWREG(x) \
296 (*((volatile uint32_t *)(x)))
297 #define HWREGH(x) \
298 (*((volatile uint16_t *)(x)))
299 #define HWREGB(x) \
300 (*((volatile uint8_t *)(x)))
301
usb_hc_low_level_init(struct usbh_bus * bus)302 void usb_hc_low_level_init(struct usbh_bus *bus)
303 {
304 #if CONFIG_SYS_CPU0
305 bk_pm_module_vote_sleep_ctrl(PM_SLEEP_MODULE_NAME_USB_1, 0x0, 0x0);
306 #endif
307 bk_analog_layer_usb_sys_related_ops(0, true);
308 bk_gpio_set_output_high(CONFIG_USB_VBAT_CONTROL_GPIO_ID);
309
310 #if NANENG_PHY_CFG
311 //NANENG_PHY_CFG_HSRX_TEST
312 HWREGB(USB_PHY_BASE + NANENG_PHY_FC_REG0F) |= (0x1 << 4);
313 //disconnect value 640mv
314 HWREGB(USB_PHY_BASE + NANENG_PHY_FC_REG0B) = 0x7C;
315 #endif
316 bk_int_isr_register(INT_SRC_USB, USBH_IRQ, NULL);
317 sys_drv_int_enable(USB_INTERRUPT_CTRL_BIT);
318 }
319
usb_hc_low_level_deinit(struct usbh_bus * bus)320 void usb_hc_low_level_deinit(struct usbh_bus *bus)
321 {
322 sys_drv_int_disable(USB_INTERRUPT_CTRL_BIT);
323 bk_int_isr_unregister(INT_SRC_USB);
324 sys_drv_dev_clk_pwr_up(CLK_PWR_ID_USB_1, CLK_PWR_CTRL_PWR_DOWN);
325 bk_analog_layer_usb_sys_related_ops(0, false);
326 }