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Searched refs:RT_BIT (Results 1 – 16 of 16) sorted by relevance

/components/drivers/include/drivers/
A Dahci.h26 #define RT_AHCI_CAP_SSC RT_BIT(14) /* Slumber capable */
28 #define RT_AHCI_CAP_SPM RT_BIT(17) /* Port Multiplier */
29 #define RT_AHCI_CAP_AHCI RT_BIT(18) /* AHCI only */
33 #define RT_AHCI_CAP_SAL RT_BIT(25) /* Activity LED */
42 #define RT_AHCI_GHC_AHCI_EN RT_BIT(31) /* AHCI enabled */
113 #define RT_AHCI_PORT_SERR_DIAG_W RT_BIT(18) /* Comm Wake */
116 #define RT_AHCI_PORT_SERR_DIAG_C RT_BIT(21) /* CRC Error */
258 #define RT_AHCI_ATA_PROT_FLAG_PIO RT_BIT(0)
259 #define RT_AHCI_ATA_PROT_FLAG_DMA RT_BIT(1)
260 #define RT_AHCI_ATA_PROT_FLAG_NCQ RT_BIT(2)
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A Dregulator.h73 #define RT_REGULATOR_MODE_FAST RT_BIT(0)
74 #define RT_REGULATOR_MODE_NORMAL RT_BIT(1)
75 #define RT_REGULATOR_MODE_IDLE RT_BIT(2)
76 #define RT_REGULATOR_MODE_STANDBY RT_BIT(3)
93 #define RT_REGULATOR_MSG_ENABLE RT_BIT(0)
94 #define RT_REGULATOR_MSG_DISABLE RT_BIT(1)
95 #define RT_REGULATOR_MSG_VOLTAGE_CHANGE RT_BIT(2)
96 #define RT_REGULATOR_MSG_VOLTAGE_CHANGE_ERR RT_BIT(3)
A Dthermal.h158 #define RT_THERMAL_MSG_EVENT_UNSPECIFIED RT_BIT(0) /* Unspecified event */
159 #define RT_THERMAL_MSG_EVENT_TEMP_SAMPLE RT_BIT(1) /* New Temperature sample */
160 #define RT_THERMAL_MSG_TRIP_VIOLATED RT_BIT(2) /* TRIP Point violation */
161 #define RT_THERMAL_MSG_TRIP_CHANGED RT_BIT(3) /* TRIP Point temperature changed…
162 #define RT_THERMAL_MSG_DEVICE_DOWN RT_BIT(4) /* Thermal device is down */
163 #define RT_THERMAL_MSG_DEVICE_UP RT_BIT(5) /* Thermal device is up after a d…
164 #define RT_THERMAL_MSG_DEVICE_POWER_CAPABILITY_CHANGED RT_BIT(6) /* Power capability changed */
165 #define RT_THERMAL_MSG_TABLE_CHANGED RT_BIT(7) /* Thermal table(s) changed */
166 #define RT_THERMAL_MSG_EVENT_KEEP_ALIVE RT_BIT(8) /* Request for user space handler…
A Ddma.h186 #define RT_DMA_F_LINEAR RT_BIT(0)
187 #define RT_DMA_F_32BITS RT_BIT(1)
188 #define RT_DMA_F_NOCACHE RT_BIT(2)
189 #define RT_DMA_F_DEVICE RT_BIT(3)
190 #define RT_DMA_F_NOMAP RT_BIT(4)
A Dpci.h45 #define PCIE_LINK_STATE_L0S RT_BIT(0)
46 #define PCIE_LINK_STATE_L1 RT_BIT(1)
47 #define PCIE_LINK_STATE_CLKPM RT_BIT(2)
48 #define PCIE_LINK_STATE_L1_1 RT_BIT(3)
49 #define PCIE_LINK_STATE_L1_2 RT_BIT(4)
50 #define PCIE_LINK_STATE_L1_1_PCIPM RT_BIT(5)
51 #define PCIE_LINK_STATE_L1_2_PCIPM RT_BIT(6)
484 #define RT_PCI_IRQ_F_LEGACY RT_BIT(0) /* Allow legacy interrupts */
485 #define RT_PCI_IRQ_F_MSI RT_BIT(1) /* Allow MSI interrupts */
486 #define RT_PCI_IRQ_F_MSIX RT_BIT(2) /* Allow MSI-X interrupts */
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A Dclk.h137 #define RT_CLK_MSG_PRE_RATE_CHANGE RT_BIT(0)
138 #define RT_CLK_MSG_POST_RATE_CHANGE RT_BIT(1)
139 #define RT_CLK_MSG_ABORT_RATE_CHANGE RT_BIT(2)
A Dmisc.h46 #define RT_BIT(n) (1UL << (n)) macro
A Dpic.h87 #define RT_PIC_F_IRQ_ROUTING RT_BIT(0) /* Routing ISR when cascade */
/components/drivers/pci/host/dw/
A Dpcie-dw.h32 #define PORT_AFR_ENTER_ASPM RT_BIT(30)
39 #define PORT_LINK_LPBK_ENABLE RT_BIT(2)
40 #define PORT_LINK_DLL_LINK_EN RT_BIT(5)
41 #define PORT_LINK_FAST_LINK_MODE RT_BIT(7)
53 #define PCIE_PORT_DEBUG1_LINK_UP RT_BIT(4)
54 #define PCIE_PORT_DEBUG1_LINK_IN_TRAINING RT_BIT(29)
58 #define PORT_LOGIC_SPEED_CHANGE RT_BIT(17)
73 #define PORT_MLTI_UPCFG_SUPPORT RT_BIT(7)
98 #define PCIE_DBI_RO_WR_EN RT_BIT(0)
104 #define PCIE_PL_CHK_REG_CHK_REG_START RT_BIT(0)
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A Dpcie-dw_host.c28 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_STATUS + res, RT_BIT(bit)); in dw_pcie_irq_ack()
47 port->irq_mask[ctrl] |= RT_BIT(bit); in dw_pcie_irq_mask()
69 port->irq_mask[ctrl] &= ~RT_BIT(bit); in dw_pcie_irq_unmask()
/components/drivers/mailbox/
A Dmailbox-pic.c68 HWREG32(pic_mbox->regs + MAILBOX_IMASK) &= ~RT_BIT(index); in pic_mbox_request()
79 HWREG32(pic_mbox->regs + MAILBOX_IMASK) |= RT_BIT(index); in pic_mbox_release()
88 while (HWREG32(pic_mbox->peer_regs + MAILBOX_ISTATE) & RT_BIT(index)) in pic_mbox_send()
93 if (HWREG32(pic_mbox->peer_regs + MAILBOX_IMASK) & RT_BIT(index)) in pic_mbox_send()
101 HWREG32(pic_mbox->peer_regs + MAILBOX_ISTATE) |= RT_BIT(index); in pic_mbox_send()
130 if (!(RT_BIT(idx) & isr)) in pic_mbox_isr()
/components/drivers/reset/
A Dreset-simple.c36 reg |= RT_BIT(offset); in reset_simple_update()
40 reg &= ~RT_BIT(offset); in reset_simple_update()
94 return !(value & RT_BIT(offset)) ^ !rsts->status_active_low; in reset_simple_status()
/components/drivers/scsi/
A Dscsi.c474 cmd.op.write_same10.config = RT_BIT(RT_SCSI_UNMAP_SHIFT); in rt_scsi_write_same10()
490 cmd.op.write_same16.config = RT_BIT(RT_SCSI_UNMAP_SHIFT); in rt_scsi_write_same16()
523 cmd.op.mode_select6.config = pf ? RT_BIT(RT_SCSI_PF_SHIFT) : 0; in rt_scsi_mode_select6()
524 cmd.op.mode_select6.config |= sp ? RT_BIT(RT_SCSI_SP_SHIFT) : 0; in rt_scsi_mode_select6()
565 cmd.op.mode_select10.config = pf ? RT_BIT(RT_SCSI_PF_SHIFT) : 0; in rt_scsi_mode_select10()
566 cmd.op.mode_select10.config |= sp ? RT_BIT(RT_SCSI_SP_SHIFT) : 0; in rt_scsi_mode_select10()
/components/drivers/pic/
A Dpic-gicv3-its.c38 #define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING RT_BIT(0)
39 #define RDIST_FLAGS_RD_TABLES_PREALLOCATED RT_BIT(1)
40 #define RDIST_FLAGS_FORCE_NON_SHAREABLE RT_BIT(2)
42 #define ITS_FLAGS_CMDQ_NEEDS_FLUSHING RT_BIT(0)
43 #define ITS_FLAGS_WORKAROUND_CAVIUM_22375 RT_BIT(1)
44 #define ITS_FLAGS_FORCE_NON_SHAREABLE RT_BIT(2)
46 #define RD_LOCAL_LPI_ENABLED RT_BIT(0)
47 #define RD_LOCAL_PENDTABLE_PREALLOCATED RT_BIT(1)
48 #define RD_LOCAL_MEMRESERVE_DONE RT_BIT(2)
/components/drivers/pci/msi/
A Dmsi.c343 msi_mask(&desc->msi, RT_BIT(pirq->irq - desc->irq), desc->pdev); in rt_pci_msi_mask_irq()
360 msi_unmask(&desc->msi, RT_BIT(pirq->irq - desc->irq), desc->pdev); in rt_pci_msi_unmask_irq()
/components/drivers/ata/
A Dahci.c609 if (!(host->ports_map & RT_BIT(i))) in rt_ahci_host_register()
725 HWREG32(host->regs + RT_AHCI_HBA_INTS) = RT_BIT(i); in rt_ahci_host_register()

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