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Searched refs:rt_phy_write (Results 1 – 3 of 3) sorted by relevance

/components/drivers/phy/
A Dphy.c114 int rt_phy_write(struct rt_phy_device *phydev, int devad, int regnum, rt_uint16_t val) in rt_phy_write() function
177 rt_phy_write(phydev, RT_MDIO_DEVAD_NONE, RT_MII_MMD_CTRL, devad); in rt_phy_mmd_start_indirect()
180 rt_phy_write(phydev, RT_MDIO_DEVAD_NONE, RT_MII_MMD_DATA, regnum); in rt_phy_mmd_start_indirect()
183 rt_phy_write(phydev, RT_MDIO_DEVAD_NONE, RT_MII_MMD_CTRL, in rt_phy_mmd_start_indirect()
218 return rt_phy_write(phydev, devad, regnum, val); in rt_phy_write_mmd()
222 return rt_phy_write(phydev, RT_MDIO_DEVAD_NONE, RT_MII_MMD_DATA, val); in rt_phy_write_mmd()
234 if (rt_phy_write(phydev, devad, RT_MII_BMCR, RT_BMCR_RESET) < 0) in rt_phy_reset()
A Dgeneral.c59 err = rt_phy_write(phydev, RT_MDIO_DEVAD_NONE, RT_MII_ADVERTISE, adv); in __genphy_config_advert()
93 err = rt_phy_write(phydev, RT_MDIO_DEVAD_NONE, RT_MII_CTRL1000, adv); in __genphy_config_advert()
113 ctl = rt_phy_write(phydev, RT_MDIO_DEVAD_NONE, RT_MII_BMCR, ctl); in __genphy_restart_aneg()
135 err = rt_phy_write(phydev, RT_MDIO_DEVAD_NONE, RT_MII_BMCR, ctl); in rt_genphy_config_aneg()
/components/drivers/include/drivers/
A Dphy.h115 int rt_phy_write(struct rt_phy_device *phydev, int devad, int regnum, rt_uint16_t val);

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