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Searched refs:ARCH_PAGE_SIZE (Results 1 – 14 of 14) sorted by relevance

/libcpu/arm/cortex-a/
A Dmmu.c308 loop_va += ARCH_PAGE_SIZE; in _kenrel_unmap_4K()
352 loop_va += ARCH_PAGE_SIZE; in _kenrel_map_4K()
353 loop_pa += ARCH_PAGE_SIZE; in _kenrel_map_4K()
378 unmap_va += ARCH_PAGE_SIZE; in rt_hw_mmu_map()
382 v_addr += ARCH_PAGE_SIZE; in rt_hw_mmu_map()
383 p_addr += ARCH_PAGE_SIZE; in rt_hw_mmu_map()
410 v_addr += ARCH_PAGE_SIZE; in rt_hw_mmu_unmap()
493 …_memcpy(mmu_table + KPTE_START, (size_t *)rt_kernel_space.page_table + KPTE_START, ARCH_PAGE_SIZE); in rt_hw_mmu_pgtbl_create()
494 rt_memset(mmu_table, 0, 3 * ARCH_PAGE_SIZE); in rt_hw_mmu_pgtbl_create()
495 rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, mmu_table, 4 * ARCH_PAGE_SIZE); in rt_hw_mmu_pgtbl_create()
A Dmmu.h85 #define ARCH_PAGE_SIZE (1 << ARCH_PAGE_SHIFT) macro
86 #define ARCH_PAGE_MASK (ARCH_PAGE_SIZE - 1)
/libcpu/aarch64/common/
A Dsetup.c221 kernel_start = RT_ALIGN_DOWN((rt_size_t)rt_kmem_v2p((void *)&_start) - 64, ARCH_PAGE_SIZE); in rt_hw_common_setup()
222 kernel_end = RT_ALIGN((rt_size_t)rt_kmem_v2p((void *)&_end), ARCH_PAGE_SIZE); in rt_hw_common_setup()
224 heap_end = RT_ALIGN(heap_start + ARCH_HEAP_SIZE, ARCH_PAGE_SIZE); in rt_hw_common_setup()
226 init_page_end = RT_ALIGN(init_page_start + ARCH_INIT_PAGE_SIZE, ARCH_PAGE_SIZE); in rt_hw_common_setup()
228 fdt_end = RT_ALIGN(fdt_start + fdt_size, ARCH_PAGE_SIZE); in rt_hw_common_setup()
258 platform_mem_region.start = RT_ALIGN_DOWN(platform_mem_region.start, ARCH_PAGE_SIZE); in rt_hw_common_setup()
259 platform_mem_region.end = RT_ALIGN(platform_mem_region.end, ARCH_PAGE_SIZE); in rt_hw_common_setup()
A Dmmu.c166 rt_memset((void *)page, 0, ARCH_PAGE_SIZE); in _kernel_map_4K()
167 rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, (void *)page, ARCH_PAGE_SIZE); in _kernel_map_4K()
235 rt_memset((char *)page, 0, ARCH_PAGE_SIZE); in _kernel_map_2M()
236 rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, (void *)page, ARCH_PAGE_SIZE); in _kernel_map_2M()
291 stride = ARCH_PAGE_SIZE; in rt_hw_mmu_map()
360 v_addr = (char *)v_addr + ARCH_PAGE_SIZE; in rt_hw_mmu_unmap()
662 rt_memset((char *)page, 0, ARCH_PAGE_SIZE); in _map_single_page_2M()
923 rt_memset((char *)tbl0, 0, ARCH_PAGE_SIZE); in rt_hw_mem_setup_early()
924 rt_memset((char *)tbl1, 0, ARCH_PAGE_SIZE); in rt_hw_mem_setup_early()
947 memset(mmu_table, 0, ARCH_PAGE_SIZE); in rt_hw_mmu_pgtbl_create()
[all …]
/libcpu/mips/gs264/
A Dmmu.c312 n += (ARCH_SECTION_SIZE/ARCH_PAGE_SIZE); in find_vaddr()
353 loop_va += ARCH_PAGE_SIZE; in check_vaddr()
397 ref_cnt = mmu_l2 + (ARCH_SECTION_SIZE/ARCH_PAGE_SIZE); in __rt_hw_mmu_unmap()
412 loop_va += ARCH_PAGE_SIZE; in __rt_hw_mmu_unmap()
464 ref_cnt = mmu_l2 + (ARCH_SECTION_SIZE/ARCH_PAGE_SIZE); in __rt_hw_mmu_map()
471 loop_va += ARCH_PAGE_SIZE; in __rt_hw_mmu_map()
472 loop_pa += ARCH_PAGE_SIZE; in __rt_hw_mmu_map()
601 ref_cnt = mmu_l2 + (ARCH_SECTION_SIZE/ARCH_PAGE_SIZE); in __rt_hw_mmu_map_auto()
609 loop_va += ARCH_PAGE_SIZE; in __rt_hw_mmu_map_auto()
624 va += ARCH_PAGE_SIZE; in __rt_hw_mmu_map_auto()
[all …]
A Dmmu.h79 #define ARCH_PAGE_SIZE (1 << ARCH_PAGE_SHIFT) macro
80 #define ARCH_PAGE_MASK (ARCH_PAGE_SIZE - 1)
/libcpu/risc-v/common64/
A Dtlb.h51 if (size <= ARCH_PAGE_SIZE) in rt_hw_tlb_invalidate_range()
A Dmmu.c203 unmap_va += ARCH_PAGE_SIZE; in rt_hw_mmu_map()
207 v_addr += ARCH_PAGE_SIZE; in rt_hw_mmu_map()
208 p_addr += ARCH_PAGE_SIZE; in rt_hw_mmu_map()
742 rt_memcpy(mmu_table, rt_kernel_space.page_table, ARCH_PAGE_SIZE); in rt_hw_mmu_pgtbl_create()
743 rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, mmu_table, ARCH_PAGE_SIZE); in rt_hw_mmu_pgtbl_create()
/libcpu/aarch64/common/include/
A Dtlb.h81 if (size <= ARCH_PAGE_SIZE) in rt_hw_tlb_invalidate_range()
A Dmmu.h82 #define ARCH_PAGE_SIZE (1 << ARCH_PAGE_SHIFT) macro
83 #define ARCH_PAGE_MASK (ARCH_PAGE_SIZE - 1)
/libcpu/risc-v/virt64/
A Driscv_mmu.h86 #define ARCH_PAGE_SIZE PAGE_SIZE macro
87 #define ARCH_PAGE_MASK (ARCH_PAGE_SIZE - 1)
/libcpu/risc-v/t-head/c908/
A Driscv_mmu.h101 #define ARCH_PAGE_SIZE PAGE_SIZE macro
102 #define ARCH_PAGE_MASK (ARCH_PAGE_SIZE - 1)
/libcpu/risc-v/t-head/c906/
A Driscv_mmu.h106 #define ARCH_PAGE_SIZE PAGE_SIZE macro
107 #define ARCH_PAGE_MASK (ARCH_PAGE_SIZE - 1)
/libcpu/aarch64/cortex-a/
A Dentry_point.S354 .space ARCH_PAGE_SIZE
357 .space 4 * ARCH_PAGE_SIZE
359 .space 24 * ARCH_PAGE_SIZE

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