Searched refs:ARCH_PAGE_TBL_SIZE (Results 1 – 5 of 5) sorted by relevance
| /libcpu/mips/gs264/ |
| A D | mmu.h | 82 #define ARCH_PAGE_TBL_SIZE (1 << ARCH_PAGE_TBL_SHIFT) macro
83 #define ARCH_PAGE_TBL_MASK (ARCH_PAGE_TBL_SIZE - 1)
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| A D | mmu.c | 444 mmu_l2 = (size_t*)rt_malloc_align(ARCH_PAGE_TBL_SIZE * 2, ARCH_PAGE_TBL_SIZE); in __rt_hw_mmu_map()
448 rt_memset(mmu_l2, 0, ARCH_PAGE_TBL_SIZE * 2); in __rt_hw_mmu_map()
450 rt_hw_cpu_dcache_clean(mmu_l2, ARCH_PAGE_TBL_SIZE); in __rt_hw_mmu_map()
589 rt_memset(mmu_l2, 0, ARCH_PAGE_TBL_SIZE * 2); in __rt_hw_mmu_map_auto()
591 rt_hw_cpu_dcache_clean(mmu_l2, ARCH_PAGE_TBL_SIZE); in __rt_hw_mmu_map_auto()
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| /libcpu/aarch64/common/include/ |
| A D | mmu.h | 85 #define ARCH_PAGE_TBL_SIZE (1 << ARCH_PAGE_TBL_SHIFT) macro
86 #define ARCH_PAGE_TBL_MASK (ARCH_PAGE_TBL_SIZE - 1)
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| /libcpu/arm/cortex-a/ |
| A D | mmu.c | 252 rt_memset(mmu_l2, 0, ARCH_PAGE_TBL_SIZE * 2); in rt_hw_mmu_ioremap_init()
254 rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, mmu_l2, ARCH_PAGE_TBL_SIZE); in rt_hw_mmu_ioremap_init()
333 rt_memset(mmu_l2, 0, ARCH_PAGE_TBL_SIZE * 2); in _kenrel_map_4K()
335 rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, mmu_l2, ARCH_PAGE_TBL_SIZE); in _kenrel_map_4K()
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| A D | mmu.h | 88 #define ARCH_PAGE_TBL_SIZE (1 << ARCH_PAGE_TBL_SHIFT) macro
89 #define ARCH_PAGE_TBL_MASK (ARCH_PAGE_TBL_SIZE - 1)
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