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/libcpu/arm/zynqmp-r5/
A Dcache.c185 register u32 CsidReg, C7Reg; in Xil_DCacheFlush() local
197 CsidReg = mfcp(XREG_CP15_CACHE_SIZE_ID); in Xil_DCacheFlush()
199 mfcp(XREG_CP15_CACHE_SIZE_ID, CsidReg); in Xil_DCacheFlush()
203 CacheSize = (CsidReg >> 13U) & 0x000001FFU; in Xil_DCacheFlush()
208 NumWays = (CsidReg & 0x000003ffU) >> 3U; in Xil_DCacheFlush()
212 LineSize = (CsidReg & 0x00000007U) + 0x00000004U; in Xil_DCacheFlush()

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