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Searched refs:CtrlReg (Results 1 – 2 of 2) sorted by relevance

/libcpu/arm/zynqmp-r5/
A Dcache.c68 register u32 CtrlReg; in Xil_DCacheEnable() local
72 CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); in Xil_DCacheEnable()
74 mfcp(XREG_CP15_SYS_CONTROL, CtrlReg); in Xil_DCacheEnable()
90 register u32 CtrlReg; in Xil_DCacheDisable() local
97 CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); in Xil_DCacheDisable()
99 mfcp(XREG_CP15_SYS_CONTROL, CtrlReg); in Xil_DCacheDisable()
104 mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); in Xil_DCacheDisable()
307 register u32 CtrlReg; in Xil_ICacheEnable() local
329 register u32 CtrlReg; in Xil_ICacheDisable() local
431 register u32 CtrlReg; in rt_hw_cpu_icache_status() local
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A Dxil_mpu.c207 u32 CtrlReg, Reg; in Xil_EnableMPU() local
211 CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); in Xil_EnableMPU()
213 mfcp(XREG_CP15_SYS_CONTROL,CtrlReg); in Xil_EnableMPU()
215 if ((CtrlReg & XREG_CP15_CONTROL_C_BIT) != 0x00000000U) { in Xil_EnableMPU()
218 if ((CtrlReg & XREG_CP15_CONTROL_I_BIT) != 0x00000000U) { in Xil_EnableMPU()
258 u32 CtrlReg, Reg; in Xil_DisableMPU() local
263 CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); in Xil_DisableMPU()
265 mfcp(XREG_CP15_SYS_CONTROL,CtrlReg); in Xil_DisableMPU()
267 if ((CtrlReg & XREG_CP15_CONTROL_C_BIT) != 0x00000000U) { in Xil_DisableMPU()
270 if ((CtrlReg & XREG_CP15_CONTROL_I_BIT) != 0x00000000U) { in Xil_DisableMPU()

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