Searched refs:GIC_DIST_CPENDSGI (Results 1 – 9 of 9) sorted by relevance
| /libcpu/arm/realview-a8-vmm/ |
| A D | gic.c | 48 #define GIC_DIST_CPENDSGI(hw_base, n) __REG32((hw_base) + 0xf10 + ((n)/4) * 4) macro
305 GIC_DIST_CPENDSGI(_gic_table[index].dist_hw_base, irq) = target_cpu << (irq % 4); in arm_gic_clear_sgi()
|
| /libcpu/aarch64/common/ |
| A D | gic.c | 59 #define GIC_DIST_CPENDSGI(hw_base, n) __REG32((hw_base) + 0xf10U + ((n)/4U) * 4U) macro
180 GIC_DIST_CPENDSGI(_gic_table[index].dist_hw_base, irq) = mask; in arm_gic_clear_pending_irq()
|
| A D | gicv3.c | 178 GIC_DIST_CPENDSGI(_gic_table[index].dist_hw_base, irq) = mask; in arm_gic_clear_pending_irq()
|
| /libcpu/arm/cortex-a/ |
| A D | gic.c | 57 #define GIC_DIST_CPENDSGI(hw_base, n) __REG32((hw_base) + 0xf10U + ((n)/4U) * 4U) macro
178 GIC_DIST_CPENDSGI(_gic_table[index].dist_hw_base, irq) = mask; in arm_gic_clear_pending_irq()
|
| A D | gicv3.h | 101 #define GIC_DIST_CPENDSGI(hw_base, n) __REG32((hw_base) + 0xf10U + ((n)/4U) * 4U) macro
|
| A D | gicv3.c | 186 GIC_DIST_CPENDSGI(_gic_table[index].dist_hw_base, irq) = mask; in arm_gic_clear_pending_irq()
|
| /libcpu/arm/cortex-r52/ |
| A D | gicv3.h | 101 #define GIC_DIST_CPENDSGI(hw_base, n) __REG32((hw_base) + 0xf10U + ((n)/4U) * 4U) macro
|
| A D | gicv3.c | 185 GIC_DIST_CPENDSGI(_gic_table[index].dist_hw_base, irq) = mask; in arm_gic_clear_pending_irq()
|
| /libcpu/aarch64/common/include/ |
| A D | gicv3.h | 100 #define GIC_DIST_CPENDSGI(hw_base, n) HWREG32((hw_base) + 0xf10U + ((n) / 4U) * 4U) macro
|
Completed in 14 milliseconds