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Searched refs:GIC_DIST_CTRL (Results 1 – 10 of 10) sorted by relevance

/libcpu/arm/zynqmp-r5/
A Dgic.c36 #define GIC_DIST_CTRL(hw_base) __REG32((hw_base) + 0x000) macro
158 GIC_DIST_CTRL(dist_base) = 0x0; in arm_gic_dist_init()
177 GIC_DIST_CTRL(dist_base) = 0x01; in arm_gic_dist_init()
/libcpu/arm/realview-a8-vmm/
A Dgic.c35 #define GIC_DIST_CTRL(hw_base) __REG32((hw_base) + 0x000) macro
224 GIC_DIST_CTRL(dist_base) = 0x0; in arm_gic_dist_init()
246 GIC_DIST_CTRL(dist_base) = 0x03; in arm_gic_dist_init()
/libcpu/aarch64/common/
A Dgic.c46 #define GIC_DIST_CTRL(hw_base) __REG32((hw_base) + 0x000U) macro
405 GIC_DIST_CTRL(dist_base) = 0x0U; in arm_gic_dist_init()
444 GIC_DIST_CTRL(dist_base) = 0x01U; in arm_gic_dist_init()
A Dgicv3.c619 GIC_DIST_CTRL(dist_base) = 0; in arm_gic_dist_init()
681 GIC_DIST_CTRL(dist_base) = GICD_CTLR_ARE_NS | GICD_CTLR_ENGRP1NS; in arm_gic_dist_init()
/libcpu/arm/cortex-a/
A Dgic.c44 #define GIC_DIST_CTRL(hw_base) __REG32((hw_base) + 0x000U) macro
398 GIC_DIST_CTRL(dist_base) = 0x0U; in arm_gic_dist_init()
425 GIC_DIST_CTRL(dist_base) = 0x01U; in arm_gic_dist_init()
A Dgicv3.h88 #define GIC_DIST_CTRL(hw_base) __REG32((hw_base) + 0x000U) macro
A Dgicv3.c511 GIC_DIST_CTRL(dist_base) = 0x0U; in arm_gic_dist_init()
560 GIC_DIST_CTRL(dist_base) = GICD_CTLR_ARE_NS | GICD_CTLR_ENGRP1NS; in arm_gic_dist_init()
/libcpu/arm/cortex-r52/
A Dgicv3.c477 GIC_DIST_CTRL(dist_base) = 0x0U; in arm_gic_dist_init()
526 GIC_DIST_CTRL(dist_base) = GICD_CTLR_ARE_NS | GICD_CTLR_ENGRP1NS; in arm_gic_dist_init()
A Dgicv3.h88 #define GIC_DIST_CTRL(hw_base) __REG32((hw_base) + 0x000U) macro
/libcpu/aarch64/common/include/
A Dgicv3.h86 #define GIC_DIST_CTRL(hw_base) HWREG32((hw_base) + 0x000U) macro

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