Searched refs:GIC_DIST_ENABLE_CLEAR (Results 1 – 10 of 10) sorted by relevance
| /libcpu/arm/zynqmp-r5/ |
| A D | gic.c | 40 #define GIC_DIST_ENABLE_CLEAR(hw_base, n) __REG32((hw_base) + 0x180 + ((n)/32) * 4) macro
72 GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; in arm_gic_ack()
86 GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; in arm_gic_mask()
174 GIC_DIST_ENABLE_CLEAR(dist_base, i) = 0xffffffff; in arm_gic_dist_init()
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| /libcpu/arm/realview-a8-vmm/ |
| A D | gic.c | 39 #define GIC_DIST_ENABLE_CLEAR(hw_base, n) __REG32((hw_base) + 0x180 + ((n)/32) * 4) macro
73 GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; in arm_gic_ack()
87 GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; in arm_gic_mask()
240 GIC_DIST_ENABLE_CLEAR(dist_base, i) = 0xffffffff; in arm_gic_dist_init()
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| /libcpu/aarch64/common/ |
| A D | gic.c | 50 #define GIC_DIST_ENABLE_CLEAR(hw_base, n) __REG32((hw_base) + 0x180U + ((n)/32U) * 4U) macro
98 GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; in arm_gic_mask()
428 GIC_DIST_ENABLE_CLEAR(dist_base, i) = 0xffffffffU; in arm_gic_dist_init()
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| A D | gicv3.c | 86 GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; in arm_gic_mask()
659 GIC_DIST_ENABLE_CLEAR(dist_base, i) = 0xffffffff; in arm_gic_dist_init()
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| /libcpu/arm/cortex-a/ |
| A D | gic.c | 48 #define GIC_DIST_ENABLE_CLEAR(hw_base, n) __REG32((hw_base) + 0x180U + ((n)/32U) * 4U) macro
96 GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; in arm_gic_mask()
414 GIC_DIST_ENABLE_CLEAR(dist_base, i) = 0xffffffffU; in arm_gic_dist_init()
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| A D | gicv3.h | 92 #define GIC_DIST_ENABLE_CLEAR(hw_base, n) __REG32((hw_base) + 0x180U + ((n)/32U) * 4U) macro
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| A D | gicv3.c | 94 GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; in arm_gic_mask()
540 GIC_DIST_ENABLE_CLEAR(dist_base, i) = 0xffffffffU; in arm_gic_dist_init()
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| /libcpu/arm/cortex-r52/ |
| A D | gicv3.c | 93 GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; in arm_gic_mask()
506 GIC_DIST_ENABLE_CLEAR(dist_base, i) = 0xffffffffU; in arm_gic_dist_init()
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| A D | gicv3.h | 92 #define GIC_DIST_ENABLE_CLEAR(hw_base, n) __REG32((hw_base) + 0x180U + ((n)/32U) * 4U) macro
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| /libcpu/aarch64/common/include/ |
| A D | gicv3.h | 91 #define GIC_DIST_ENABLE_CLEAR(hw_base, n) HWREG32((hw_base) + 0x180U + ((n) / 32U) * 4U) macro
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