Searched refs:GIC_DIST_IGROUP (Results 1 – 10 of 10) sorted by relevance
| /libcpu/arm/realview-a8-vmm/ |
| A D | gic.c | 37 #define GIC_DIST_IGROUP(hw_base, n) __REG32((hw_base) + 0x080 + ((n)/32) * 4) macro
243 GIC_DIST_IGROUP(dist_base, i) = 0xffffffff; in arm_gic_dist_init()
279 GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, in arm_gic_set_group()
284 GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, in arm_gic_set_group()
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| /libcpu/arm/cortex-a/ |
| A D | gic.c | 46 #define GIC_DIST_IGROUP(hw_base, n) __REG32((hw_base) + 0x080U + ((n)/32U) * 4U) macro
352 igroupr = GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq); in arm_gic_set_group()
357 GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq) = igroupr; in arm_gic_set_group()
367 return (GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; in arm_gic_get_group()
419 GIC_DIST_IGROUP(dist_base, i) = 0xffffffff; in arm_gic_dist_init()
422 GIC_DIST_IGROUP(dist_base, i) = 0U; in arm_gic_dist_init()
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| A D | gicv3.c | 440 igroupr = GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq); in arm_gic_set_group()
445 GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq) = igroupr; in arm_gic_set_group()
455 return (GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; in arm_gic_get_group()
546 GIC_DIST_IGROUP(dist_base, i) = 0xffffffffU; in arm_gic_dist_init()
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| A D | gicv3.h | 90 #define GIC_DIST_IGROUP(hw_base, n) __REG32((hw_base) + 0x080U + ((n)/32U) * 4U) macro
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| /libcpu/aarch64/common/ |
| A D | gic.c | 48 #define GIC_DIST_IGROUP(hw_base, n) __REG32((hw_base) + 0x080U + ((n)/32U) * 4U) macro
355 igroupr = GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq); in arm_gic_set_group()
360 GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq) = igroupr; in arm_gic_set_group()
370 return (GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; in arm_gic_get_group()
440 GIC_DIST_IGROUP(dist_base, i) = 0U; in arm_gic_dist_init()
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| A D | gicv3.c | 540 igroupr = GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq); in arm_gic_set_group()
545 GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq) = igroupr; in arm_gic_set_group()
555 return (GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq) >> (irq % 32)) & 0x1UL; in arm_gic_get_group()
666 GIC_DIST_IGROUP(dist_base, i) = 0xffffffff; in arm_gic_dist_init()
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| /libcpu/arm/cortex-r52/ |
| A D | gicv3.c | 406 igroupr = GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq); in arm_gic_set_group()
411 GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq) = igroupr; in arm_gic_set_group()
421 return (GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; in arm_gic_get_group()
512 GIC_DIST_IGROUP(dist_base, i) = 0xffffffffU; in arm_gic_dist_init()
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| A D | gicv3.h | 90 #define GIC_DIST_IGROUP(hw_base, n) __REG32((hw_base) + 0x080U + ((n)/32U) * 4U) macro
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| /libcpu/arm/zynqmp-r5/ |
| A D | gic.c | 38 #define GIC_DIST_IGROUP(hw_base, n) __REG32((hw_base) + 0x080 + ((n)/32) * 4) macro
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| /libcpu/aarch64/common/include/ |
| A D | gicv3.h | 89 #define GIC_DIST_IGROUP(hw_base, n) HWREG32((hw_base) + 0x080U + ((n) / 32U) * 4U) macro
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