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Searched refs:GIC_RDISTSGI_ICENABLER0 (Results 1 – 6 of 6) sorted by relevance

/libcpu/arm/cortex-r52/
A Dgicv3.c89 GIC_RDISTSGI_ICENABLER0(_gic_table[index].redist_hw_base[cpu_id]) = mask; in arm_gic_mask()
569 GIC_RDISTSGI_ICENABLER0(base) = 0xFFFFFFFF; in arm_gic_redist_init()
A Dgicv3.h127 #define GIC_RDISTSGI_ICENABLER0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x180U) macro
/libcpu/arm/cortex-a/
A Dgicv3.h127 #define GIC_RDISTSGI_ICENABLER0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x180U) macro
A Dgicv3.c90 GIC_RDISTSGI_ICENABLER0(_gic_table[index].redist_hw_base[cpu_id]) = mask; in arm_gic_mask()
601 GIC_RDISTSGI_ICENABLER0(base) = 0xFFFFFFFF; in arm_gic_redist_init()
/libcpu/aarch64/common/include/
A Dgicv3.h124 #define GIC_RDISTSGI_ICENABLER0(hw_base) HWREG32((hw_base) + GIC_RSGI_OFFSET + 0x180U) macro
/libcpu/aarch64/common/
A Dgicv3.c82 GIC_RDISTSGI_ICENABLER0(_gic_table[index].redist_hw_base[cpu_id]) = mask; in arm_gic_mask()
717 GIC_RDISTSGI_ICENABLER0(redist_base) = 0xffffffff; in arm_gic_redist_init()

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