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Searched refs:ICC_SRE_EL1 (Results 1 – 2 of 2) sorted by relevance

/libcpu/aarch64/common/include/
A Dgicv3.h45 #define ICC_SRE_EL1 "S3_0_C12_C12_5" macro
/libcpu/aarch64/common/
A Dgicv3.c323 SET_GICV3_REG(ICC_SRE_EL1, value); in arm_gic_set_system_register_enable_mask()
332 GET_GICV3_REG(ICC_SRE_EL1, value); in arm_gic_get_system_register_enable_mask()

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