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Searched refs:MTC0 (Results 1 – 4 of 4) sorted by relevance

/libcpu/mips/common/
A Dentry_gcc.S34 MTC0 zero, CP0_CAUSE
35 MTC0 zero, CP0_STATUS # Set CPU to disable interrupt.
40 MTC0 t0, CP0_STATUS
A Dasm.h206 #define MTC0 dmtc0 macro
300 #define MTC0 mtc0 macro
A Dcontext_gcc.S29 MTC0 ra, CP0_EPC
A Dstackframe.h28 MTC0 v1, CP0_STATUS
133 MTC0 v1, CP0_STATUS
213 MTC0 v1, CP0_EPC

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