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Searched refs:Offset (Results 1 – 19 of 19) sorted by relevance

/libcpu/arm/s3c44b0/
A Dstart_rvds.S71 SYSCFG_OFS EQU 0x00 ; SYSCFG Offset
72 NCACHBE0_OFS EQU 0x04 ; NCACHBE0 Offset
73 NCACHBE1_OFS EQU 0x08 ; NCACHBE0 Offset
75 SBUSCON_OFS EQU 0x00 ; SBUSCON Offset
150 PLLCON_OFS EQU 0x00 ; PLLCON Offset
151 CLKCON_OFS EQU 0x04 ; CLKCON Offset
199 WTCON_OFS EQU 0x00 ; WTCON Offset
200 WTDAT_OFS EQU 0x04 ; WTDAT Offset
201 WTCNT_OFS EQU 0x08 ; WTCNT Offset
544 PUPC_OFS EQU 0x18 ; PUPC Offset
[all …]
/libcpu/arm/s3c24x0/
A Dstart_rvds.S99 WTCON_OFS EQU 0x00 ; Watchdog Timer Control Register Offset
124 LOCKTIME_OFS EQU 0x00 ; PLL Lock Time Count Register Offset
125 MPLLCON_OFS EQU 0x04 ; MPLL Configuration Register Offset
126 UPLLCON_OFS EQU 0x08 ; UPLL Configuration Register Offset
127 CLKCON_OFS EQU 0x0C ; Clock Generator Control Reg Offset
128 CLKSLOW_OFS EQU 0x10 ; Clock Slow Control Register Offset
129 CLKDIVN_OFS EQU 0x14 ; Clock Divider Control Register Offset
130 CAMDIVN_OFS EQU 0x18 ; Camera Clock Divider Register Offset
496 GPCON_OFS EQU 0x00 ; Control Register Offset
497 GPDAT_OFS EQU 0x04 ; Data Register Offset
[all …]
/libcpu/arm/lpc214x/
A Dstart_rvds.S110 PLLCON_OFS EQU 0x00 ; PLL Control Offset
111 PLLCFG_OFS EQU 0x04 ; PLL Configuration Offset
112 PLLSTAT_OFS EQU 0x08 ; PLL Status Offset
113 PLLFEED_OFS EQU 0x0C ; PLL Feed Offset
134 MAMCR_OFS EQU 0x00 ; MAM Control Offset
135 MAMTIM_OFS EQU 0x04 ; MAM Timing Offset
155 BCFG0_OFS EQU 0x00 ; BCFG0 Offset
156 BCFG1_OFS EQU 0x04 ; BCFG1 Offset
157 BCFG2_OFS EQU 0x08 ; BCFG2 Offset
158 BCFG3_OFS EQU 0x0C ; BCFG3 Offset
/libcpu/arm/lpc24xx/
A Dstart_rvds.S127 PLLCON_OFS EQU 0x80 ; PLL Control Offset
128 PLLCFG_OFS EQU 0x84 ; PLL Configuration Offset
129 PLLSTAT_OFS EQU 0x88 ; PLL Status Offset
130 PLLFEED_OFS EQU 0x8C ; PLL Feed Offset
351 MAMCR_OFS EQU 0x00 ; MAM Control Offset
352 MAMTIM_OFS EQU 0x04 ; MAM Timing Offset
373 PINSEL0_OFS EQU 0x00 ; PINSEL0 Address Offset
374 PINSEL1_OFS EQU 0x04 ; PINSEL1 Address Offset
375 PINSEL2_OFS EQU 0x08 ; PINSEL2 Address Offset
376 PINSEL3_OFS EQU 0x0C ; PINSEL3 Address Offset
[all …]
/libcpu/arm/AT91SAM7S/
A Dstart_rvds.S86 RSTC_MR EQU 0x08 ; RSTC_MR Offset
102 EFC0_FMR EQU 0x60 ; EFC0_FMR Offset
103 EFC1_FMR EQU 0x70 ; EFC1_FMR Offset
132 WDT_MR EQU 0x04 ; WDT_MR Offset
150 PMC_MOR EQU 0x20 ; PMC_MOR Offset
151 PMC_MCFR EQU 0x24 ; PMC_MCFR Offset
152 PMC_PLLR EQU 0x2C ; PMC_PLLR Offset
153 PMC_MCKR EQU 0x30 ; PMC_MCKR Offset
154 PMC_SR EQU 0x68 ; PMC_SR Offset
350 MC_RCR EQU 0x00 ; MC_RCR Offset
/libcpu/arm/AT91SAM7X/
A Dstart_rvds.S89 RSTC_MR EQU 0x08 ; RSTC_MR Offset
105 EFC0_FMR EQU 0x60 ; EFC0_FMR Offset
106 EFC1_FMR EQU 0x70 ; EFC1_FMR Offset
135 WDT_MR EQU 0x04 ; WDT_MR Offset
153 PMC_MOR EQU 0x20 ; PMC_MOR Offset
154 PMC_MCFR EQU 0x24 ; PMC_MCFR Offset
155 PMC_PLLR EQU 0x2C ; PMC_PLLR Offset
156 PMC_MCKR EQU 0x30 ; PMC_MCKR Offset
157 PMC_SR EQU 0x68 ; PMC_SR Offset
353 MC_RCR EQU 0x00 ; MC_RCR Offset
/libcpu/arm/zynqmp-r5/
A Dmpu.c111 u32 RegNum = 0, i, Offset = 0; in Init_MPU() local
128 Offset = XPAR_PSU_R5_DDR_0_S_AXI_BASEADDR; in Init_MPU()
129 if (region_size[i].size > (size + Offset + 1)) { in Init_MPU()
/libcpu/arm/cortex-m3/
A Dcontext_iar.S19 SCB_VTOR EQU 0xE000ED08 ; Vector Table Offset Register
A Dcontext_rvds.S18 SCB_VTOR EQU 0xE000ED08 ; Vector Table Offset Register
/libcpu/arm/cortex-m0/
A Dcontext_iar.S19 SCB_VTOR EQU 0xE000ED08 ; Vector Table Offset Register
A Dcontext_rvds.S19 SCB_VTOR EQU 0xE000ED08 ; Vector Table Offset Register
/libcpu/arm/cortex-m23/
A Dcontext_iar.S20 SCB_VTOR EQU 0xE000ED08 ; Vector Table Offset Register
A Dcontext_rvds.S20 SCB_VTOR EQU 0xE000ED08 ; Vector Table Offset Register
/libcpu/arm/cortex-m7/
A Dcontext_iar.S21 SCB_VTOR EQU 0xE000ED08 ; Vector Table Offset Register
A Dcontext_rvds.S20 SCB_VTOR EQU 0xE000ED08 ; Vector Table Offset Register
/libcpu/arm/cortex-m4/
A Dcontext_iar.S22 SCB_VTOR EQU 0xE000ED08 ; Vector Table Offset Register
A Dcontext_rvds.S21 SCB_VTOR EQU 0xE000ED08 ; Vector Table Offset Register
/libcpu/arm/cortex-m33/
A Dcontext_iar.S21 SCB_VTOR EQU 0xE000ED08 ; Vector Table Offset Register
A Dcontext_rvds.S20 SCB_VTOR EQU 0xE000ED08 ; Vector Table Offset Register

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