Home
last modified time | relevance | path

Searched refs:RT_CPUS_NR (Results 1 – 12 of 12) sorted by relevance

/libcpu/aarch64/common/
A Dcpu.c28 ((((cpuid) >= 0) && ((cpuid) < RT_CPUS_NR)) ? rt_cpu_mpidr_early[cpuid] : ID_ERROR)
30 ((((cpuid) >= 0) && ((cpuid) < RT_CPUS_NR)) ? (rt_cpu_mpidr_early[cpuid] = (hwid)) : ID_ERROR)
32 ((((cpuid) >= 0) && ((cpuid) < RT_CPUS_NR)) ? _cpu_node[cpuid] : NULL)
34 ((((cpuid) >= 0) && ((cpuid) < RT_CPUS_NR)) ? (_cpu_node[cpuid] = node) : NULL)
37 struct cpu_ops_t *cpu_ops_tbl[RT_CPUS_NR];
41 rt_uint64_t rt_cpu_mpidr_early[RT_CPUS_NR] rt_weak = {[0 ... RT_CPUS_NR - 1] = ID_ERROR};
54 [RT_CPUS_NR] = 0
157 if (num_cpus > RT_CPUS_NR) in _cpus_init_data_hardcoded()
159 LOG_W("num_cpus (%d) greater than RT_CPUS_NR (%d)\n", num_cpus, RT_CPUS_NR); in _cpus_init_data_hardcoded()
160 num_cpus = RT_CPUS_NR; in _cpus_init_data_hardcoded()
[all …]
A Dinterrupt.c22 #ifndef RT_CPUS_NR
23 #define RT_CPUS_NR 1 macro
395 rt_uint32_t gicv3_cpu_mask[(RT_CPUS_NR + 31) >> 5]; in rt_hw_ipi_send()
415 for (int i = 0; i < RT_CPUS_NR; i++) in list_isr()
427 for (int i = 0; i < RT_CPUS_NR; i++) in list_isr()
440 for (int i = 0; i < RT_CPUS_NR; i++) in list_isr()
A Dcpu_spin_table.c25 static rt_uint64_t cpu_release_addr[RT_CPUS_NR];
A Dsetup.c52 [RT_CPUS_NR] = 0,
63 static struct rt_ofw_node *cpu_np[RT_CPUS_NR] = { };
75 static rt_ubase_t loops_per_tick[RT_CPUS_NR];
184 if (++i >= RT_CPUS_NR) in cpu_info_init()
A Dgicv3.c39 #define RT_CPUS_NR 1 macro
390 rt_uint32_t cpu_mask[(RT_CPUS_NR + 31) >> 5];
394 static struct gicv3_sgi_aff sgi_aff_table[RT_CPUS_NR];
418 for (i = 0; i < RT_CPUS_NR; i++) in gicv3_sgi_init()
427 return (RT_CPUS_NR + 31) >> 5; in gicv3_sgi_init()
A Dpsci.c103 if (cpuid < RT_CPUS_NR) in psci_cpu_on()
160 if (cpuid < RT_CPUS_NR) in psci_migrate()
A Dcpu_gcc.S71 #if RT_CPUS_NR > 1
/libcpu/arm/cortex-r52/
A Dgicv3.c20 #ifndef RT_CPUS_NR
21 #define RT_CPUS_NR 1 macro
27 rt_uint32_t redist_hw_base[RT_CPUS_NR]; /* the pointer of the gic redistributor */
88 RT_ASSERT((cpu_id) < RT_CPUS_NR); in arm_gic_mask()
109 RT_ASSERT((cpu_id) < RT_CPUS_NR); in arm_gic_umask()
270 RT_ASSERT((cpu_id) < RT_CPUS_NR); in arm_gic_set_priority()
297 RT_ASSERT((cpu_id) < RT_CPUS_NR); in arm_gic_get_priority()
435 RT_ASSERT((cpu_id) < RT_CPUS_NR); in arm_gicv3_wait_rwp()
534 RT_ASSERT((cpu_id) < RT_CPUS_NR); in arm_gic_redist_address_set()
543 RT_ASSERT((cpu_id) < RT_CPUS_NR); in arm_gic_cpu_interface_address_set()
[all …]
/libcpu/arm/cortex-a/
A Dgicv3.c20 #ifndef RT_CPUS_NR
21 #define RT_CPUS_NR 1 macro
27 rt_uint32_t redist_hw_base[RT_CPUS_NR]; /* the pointer of the gic redistributor */
89 RT_ASSERT((cpu_id) < RT_CPUS_NR); in arm_gic_mask()
110 RT_ASSERT((cpu_id) < RT_CPUS_NR); in arm_gic_umask()
271 RT_ASSERT((cpu_id) < RT_CPUS_NR); in arm_gic_set_priority()
298 RT_ASSERT((cpu_id) < RT_CPUS_NR); in arm_gic_get_priority()
469 RT_ASSERT((cpu_id) < RT_CPUS_NR); in arm_gicv3_wait_rwp()
568 RT_ASSERT((cpu_id) < RT_CPUS_NR); in arm_gic_redist_address_set()
577 RT_ASSERT((cpu_id) < RT_CPUS_NR); in arm_gic_cpu_interface_address_set()
[all …]
A Dstart_gcc.S665 #if defined(RT_USING_SMP) && (RT_CPUS_NR > 1)
666 .space ((RT_CPUS_NR - 1) * ARM_CPU_STACK_SIZE)
672 #if defined(RT_USING_SMP) && (RT_CPUS_NR > 1)
673 .space ((RT_CPUS_NR - 1) * ARM_CPU_STACK_SIZE)
680 #if defined(RT_USING_SMP) && (RT_CPUS_NR > 1)
681 .space ((RT_CPUS_NR - 1) * ARM_CPU_STACK_SIZE)
687 #if defined(RT_USING_SMP) && (RT_CPUS_NR > 1)
688 .space ((RT_CPUS_NR - 1) * ARM_CPU_STACK_SIZE)
/libcpu/aarch64/cortex-a/
A Dentry_point.S341 #if defined(RT_USING_SMP) && RT_CPUS_NR > 1
342 .space (ARCH_SECONDARY_CPU_STACK_SIZE * (RT_CPUS_NR - 1))
/libcpu/aarch64/common/include/
A Dgicv3.h23 #define ARM_GIC_CPU_NUM RT_CPUS_NR

Completed in 19 milliseconds