Searched refs:Reg (Results 1 – 3 of 3) sorted by relevance
207 u32 CtrlReg, Reg; in Xil_EnableMPU() local229 Reg = mfcp(XREG_CP15_SYS_CONTROL); in Xil_EnableMPU()231 mfcp(XREG_CP15_SYS_CONTROL,Reg); in Xil_EnableMPU()233 Reg |= 0x00000001U; in Xil_EnableMPU()235 mtcp(XREG_CP15_SYS_CONTROL, Reg); in Xil_EnableMPU()258 u32 CtrlReg, Reg; in Xil_DisableMPU() local283 Reg = mfcp(XREG_CP15_SYS_CONTROL); in Xil_DisableMPU()285 mfcp(XREG_CP15_SYS_CONTROL,Reg); in Xil_DisableMPU()287 Reg &= ~(0x00000001U); in Xil_DisableMPU()289 mtcp(XREG_CP15_SYS_CONTROL, Reg); in Xil_DisableMPU()
131 CCLKCFG_OFS EQU 0x104 ; CPU Clock Divider Reg Offset132 USBCLKCFG_OFS EQU 0x108 ; USB Clock Divider Reg Offset133 CLKSRCSEL_OFS EQU 0x10C ; Clock Source Sel Reg Offset134 SCS_OFS EQU 0x1A0 ; Sys Control and Status Reg Offset135 PCLKSEL0_OFS EQU 0x1A8 ; Periph Clock Sel Reg 0 Offset136 PCLKSEL1_OFS EQU 0x1AC ; Periph Clock Sel Reg 0 Offset138 PCON_OFS EQU 0x0C0 ; Power Mode Control Reg Offset139 PCONP_OFS EQU 0x0C4 ; Power Control for Periphs Reg Offset
127 CLKCON_OFS EQU 0x0C ; Clock Generator Control Reg Offset
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