Searched refs:SET_GICV3_REG (Results 1 – 2 of 2) sorted by relevance
| /libcpu/aarch64/common/ |
| A D | gicv3.c | 66 SET_GICV3_REG(ICC_EOIR1_EL1, (rt_base_t)irq); in arm_gic_ack()
323 SET_GICV3_REG(ICC_SRE_EL1, value); in arm_gic_set_system_register_enable_mask()
342 SET_GICV3_REG(ICC_PMR_EL1, priority); in arm_gic_set_interface_prior_mask()
359 SET_GICV3_REG(ICC_BPR1_EL1, binary_point); in arm_gic_set_binary_point()
439 … SET_GICV3_REG(ICC_SGI1R_EL1, sgi_aff_table[i].aff | int_id | sgi_aff_table[i].target_list); in gicv3_sgi_send()
493 SET_GICV3_REG(ICC_SGI1R_EL1, (0x10000000000ULL) | int_id); in arm_gic_send_affinity_sgi()
750 SET_GICV3_REG(ICC_CTLR_EL1, 0l); in arm_gic_cpu_init()
756 SET_GICV3_REG(ICC_IGRPEN1_EL1, value); in arm_gic_cpu_init()
763 SET_GICV3_REG(ICC_CTLR_EL1, value); in arm_gic_cpu_init()
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| /libcpu/aarch64/common/include/ |
| A D | gicv3.h | 29 #define SET_GICV3_REG(reg, in) __asm__ volatile ("msr " reg ", %0"::"r"(in):"memory"); macro
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