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Searched refs:SP (Results 1 – 25 of 26) sorted by relevance

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/libcpu/blackfin/bf53x/
A Dcontext_vdsp.S49 [ -- SP ] = R0;
50 [ -- SP ] = P1;
52 [ -- SP ] = R1;
53 [ -- SP ] = R2;
54 [ -- SP ] = P0;
55 [ -- SP ] = P2;
60 [ -- SP ] = R1;
62 [ -- SP ] = FP;
63 [ -- SP ] = I0;
64 [ -- SP ] = I1;
[all …]
/libcpu/ti-dsp/c6x/
A Dcontextinc.asm29 LDW .D2T2 *++SP[2],B0
33 ||[!B0] STDW .D2T2 SP:DP,*--SP[1] ; kernel: nest interrupt save(not support)
35 SUBAW .D2 SP,2,SP
37 ADD .D1X SP,-8,A15
91 ADDAW .D1X SP,30,A15
131 MV .D2X A15,SP
134 || ADDAW .D1X SP,6,A14
138 LDDW .D2T2 *+SP[1],SP:DP
143 STDW .D2T2 SP:DP,*--SP[1]
144 SUBAW .D2 SP,2,SP
[all …]
A Dcontext.asm20 SP .set B15 label
123 SUBAW .D2 SP,2,SP
124 ADD .D1X SP,-8,A15
125 || STDW .D2T1 A15:A14,*SP--[3] ; Store A15:A14
127 STDW .D2T2 B13:B12,*SP--[1] ; Store B13:B12
130 STDW .D2T2 B11:B10,*SP--[1] ; Store B11:B10
133 STDW .D2T2 B13:B12,*SP--[1] ; Store PC:CSR
138 STDW .D2T2 B11:B10,*SP--[1] ; Store RILC:ILC
142 STDW .D2T1 A3:A2,*SP--[1] ; Store TSR:stack type
143 STW SP,*A4 ; Save thread's stack pointer
A Dintexc.asm19 SP .set B15 label
122 [!B2] ADDAW .D2 SP,2,B1
143 ADDAW .D2 SP,2,B1
/libcpu/aarch64/common/up/
A Dcontext_gcc.h56 LDP X29, X30, [SP], #0x10
58 LDP X28, X29, [SP], #0x10
61 LDP X28, X29, [SP], #0x10
62 LDP X26, X27, [SP], #0x10
63 LDP X24, X25, [SP], #0x10
71 LDP X8, X9, [SP], #0x10
72 LDP X6, X7, [SP], #0x10
73 LDP X4, X5, [SP], #0x10
74 LDP X2, X3, [SP], #0x10
75 LDP X0, X1, [SP], #0x10
[all …]
/libcpu/arm/arm926/
A Dstart_rvds.S180 SUB SP, SP, #S_FRAME_SIZE
182 ADD R8, SP, #S_PC
183 STMDB R8, {SP, LR} ; Calling SP, LR
188 MOV R0, SP
201 SUB SP, SP, #S_FRAME_SIZE
203 ADD R8, SP, #S_PC
204 STMDB R8, {SP, LR} ; Calling SP, LR
209 MOV R0, SP
218 STMFD SP!, {R0-R7,LR}
220 LDMFD SP!, {R0-R7,LR}
[all …]
A Dstart_iar.S137 LDR SP, =SVC_STACK_START
192 SUB SP, SP, #S_FRAME_SIZE
194 ADD R8, SP, #S_PC
195 STMDB R8, {SP, LR} ; Calling SP, LR
200 MOV R0, SP
210 SUB SP, SP, #S_FRAME_SIZE
212 ADD R8, SP, #S_PC
213 STMDB R8, {SP, LR} ; Calling SP, LR
218 MOV R0, SP
225 STMFD SP!, {R0-R12,LR}
[all …]
A Dcontext_gcc.S39 STMFD SP!, {LR} @; push pc (lr should be pushed in place of pc)
40 STMFD SP!, {R0-R12, LR} @; push lr & register file
42 STMFD SP!, {R4} @; push cpsr
43 STR SP, [R0] @; store sp in preempted tasks tcb
44 LDR SP, [R1] @; get new task stack pointer
45 LDMFD SP!, {R4} @; pop new task spsr
47 LDMFD SP!, {R0-R12, LR, PC}^ @; pop new task r0-r12, lr & pc
55 LDR SP, [R0] @; get new task stack pointer
56 LDMFD SP!, {R4} @; pop new task cpsr
58 LDMFD SP!, {R0-R12, LR, PC}^ @; pop new task r0-r12, lr & pc
A Dcontext_iar.S40 STMFD SP!, {LR} ; push pc (lr should be pushed in place of PC)
41 STMFD SP!, {R0-R12, LR} ; push lr & register file
43 STMFD SP!, {R4} ; push cpsr
44 STR SP, [R0] ; store sp in preempted tasks TCB
45 LDR SP, [R1] ; get new task stack pointer
46 LDMFD SP!, {R4} ; pop new task spsr
48 LDMFD SP!, {R0-R12, LR, PC}^ ; pop new task r0-r12, lr & pc
56 LDR SP, [R0] ; get new task stack pointer
57 LDMFD SP!, {R4} ; pop new task spsr
59 LDMFD SP!, {R0-R12, LR, PC}^ ; pop new task r0-r12, lr & pc
/libcpu/arm/cortex-r52/
A Dbacktrace.c65 SP = 13, enumerator
239 ctrl->vrs[SP] = (unsigned long)vsp; in unwind_exec_pop_subset_r4_to_r13()
259 ctrl->vrs[SP] = (unsigned long)vsp; in unwind_exec_pop_r4_to_rN()
279 ctrl->vrs[SP] = (unsigned long)vsp; in unwind_exec_pop_subset_r0_to_r3()
295 ctrl->vrs[SP] += ((insn & 0x3f) << 2) + 4; in unwind_exec_insn()
297 ctrl->vrs[SP] -= ((insn & 0x3f) << 2) + 4; in unwind_exec_insn()
317 ctrl->vrs[SP] = ctrl->vrs[insn & 0x0f]; in unwind_exec_insn()
350 ctrl->vrs[SP] += 0x204 + (uleb128 << 2); in unwind_exec_insn()
416 ctrl.vrs[SP] = frame->sp; in unwind_frame()
464 if (ctrl.vrs[SP] < low || ctrl.vrs[SP] >= ctrl.sp_high) in unwind_frame()
[all …]
A Dcontext_gcc.S195 @ mode so there is no need to update SP.
196 SUB r1, sp, #16 @ save the right SP value in r1, so we could restore r0-r3.
A Dcontext_iar.S203 ; mode so there is no need to update SP.
204 SUB r1, sp, #16 ; save the right SP value in r1, so we could restore r0-r3.
/libcpu/arm/cortex-a/
A Dbacktrace.c64 SP = 13, enumerator
238 ctrl->vrs[SP] = (unsigned long)vsp; in unwind_exec_pop_subset_r4_to_r13()
258 ctrl->vrs[SP] = (unsigned long)vsp; in unwind_exec_pop_r4_to_rN()
278 ctrl->vrs[SP] = (unsigned long)vsp; in unwind_exec_pop_subset_r0_to_r3()
294 ctrl->vrs[SP] += ((insn & 0x3f) << 2) + 4; in unwind_exec_insn()
296 ctrl->vrs[SP] -= ((insn & 0x3f) << 2) + 4; in unwind_exec_insn()
316 ctrl->vrs[SP] = ctrl->vrs[insn & 0x0f]; in unwind_exec_insn()
349 ctrl->vrs[SP] += 0x204 + (uleb128 << 2); in unwind_exec_insn()
415 ctrl.vrs[SP] = frame->sp; in unwind_frame()
463 if (ctrl.vrs[SP] < low || ctrl.vrs[SP] >= ctrl.sp_high) in unwind_frame()
[all …]
/libcpu/arm/am335x/
A Dcontext_iar.S40 STMFD SP!, {LR} ; push pc (lr should be pushed in place of PC)
41 STMFD SP!, {R0-R12, LR} ; push lr & register file
/libcpu/arm/cortex-m33/
A Dsyscall_rvds.S30 MOV R4, R1 ; copy thread SP to R4
51 ; get SP, save to R1
/libcpu/arm/lpc214x/
A Dstart_rvds.S375 MOV SP, R0
380 MOV SP, R0
385 MOV SP, R0
390 MOV SP, R0
395 MOV SP, R0
407 ; MOV SP, R0
408 ; SUB SL, SP, #USR_Stack_Size
/libcpu/ti-dsp/c28x/
A Dcontext.s104 ; SP[4] --> to
116 MOVL XAR4, *-SP[4]
136 ; SP[4] --> to
142 MOVL XAR4, *-SP[4]
/libcpu/arm/AT91SAM7S/
A Dstart_rvds.S365 MOV SP, R0
370 MOV SP, R0
375 MOV SP, R0
380 MOV SP, R0
385 MOV SP, R0
397 ;MOV SP, R0
398 ;SUB SL, SP, #USR_Stack_Size
/libcpu/arm/sep4020/
A Dstart_rvds.S173 LDR SP, =Svc_Stack_Top ;init SP_svc
177 LDR SP, =Irq_Stack_Top
181 LDR SP, =Unused_Stack_Top
185 LDR SP, =Unused_Stack_Top
189 LDR SP, =Unused_Stack_Top
194 LDR SP, =Unused_Stack_Top
/libcpu/arm/s3c44b0/
A Dstart_rvds.S938 MOV SP, R0
943 MOV SP, R0
948 MOV SP, R0
953 MOV SP, R0
958 MOV SP, R0
969 ; MOV SP, R0
970 ; SUB SL, SP, #USR_Stack_Size
/libcpu/arm/AT91SAM7X/
A Dstart_rvds.S368 MOV SP, R0
373 MOV SP, R0
378 MOV SP, R0
383 MOV SP, R0
388 MOV SP, R0
400 ;MOV SP, R0
401 ;SUB SL, SP, #USR_Stack_Size
/libcpu/arm/cortex-r4/
A Dcontext_ccs.asm204 ; mode so there is no need to update SP.
205 SUB r1, sp, #16 ; save the right SP value in r1, so we could restore r0-r3.
A Dcontext_gcc.S198 @ mode so there is no need to update SP.
199 SUB r1, sp, #16 @ save the right SP value in r1, so we could restore r0-r3.
/libcpu/arm/s3c24x0/
A Dstart_rvds.S1064 MOV SP, R0
1069 MOV SP, R0
1074 MOV SP, R0
1079 MOV SP, R0
1084 MOV SP, R0
1089 MOV SP, R0
1090 SUB SL, SP, #USR_Stack_Size
/libcpu/v850/70f34/
A Dmacdefs.inc102 cmp 1, r2 ;If OSNesting==1 save SP in current TCB

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