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Searched refs:TSR (Results 1 – 6 of 6) sorted by relevance

/libcpu/ti-dsp/c6x/
A Dcontext.asm41 MVC .S2 TSR,B0
45 MVC .S2 B0,TSR ; Set GEE and XEN in TSR
134 || MVC .S2 TSR,B5
142 STDW .D2T1 A3:A2,*SP--[1] ; Store TSR:stack type
A Dinterrupt.c67 TSR = TSR | 1; in rt_hw_interrupt_umask()
A Dintexc.asm112 || MVC .S2 TSR,B1
115 MVC .S2 B1,TSR
A Dc66xx.h17 extern __cregister volatile unsigned int TSR; /* Task State Register */
A Dcontextinc.asm83 STDW .D2T1 A5:A4,*SP--[1] ; save TSR and orig A4(stack type)
87 LDDW .D2T2 *++SP[1],B9:B8 ; get TSR (B9)
191 STDW .D2T1 A5:A4,*SP--[1] ; save TSR and orig A4(stack type)
/libcpu/ppc/ppc405/include/asm/
A Dprocessor.h642 #define TSR SPRN_TSR /* Timer Status Register */ macro

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