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Searched refs:VEC_IMM_SEW_8 (Results 1 – 2 of 2) sorted by relevance

/libcpu/risc-v/vector/rvv-1.0/
A Drvv_context.h66 VEC_CONFIG_SETVLI(t2, x0, VEC_IMM_SEW_8, VEC_IMM_LMUL_8)
88 VEC_CONFIG_SETVLI(t2, x0, VEC_IMM_SEW_8, VEC_IMM_LMUL_8)
A Dvector_encoding.h28 #define VEC_IMM_SEW_8 e8 macro

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