Home
last modified time | relevance | path

Searched refs:XREG_CP15_CACHE_SIZE_ID (Results 1 – 2 of 2) sorted by relevance

/libcpu/arm/zynqmp-r5/
A Dcache.c197 CsidReg = mfcp(XREG_CP15_CACHE_SIZE_ID); in Xil_DCacheFlush()
199 mfcp(XREG_CP15_CACHE_SIZE_ID, CsidReg); in Xil_DCacheFlush()
A Dxreg_cortexr5.h206 #define XREG_CP15_CACHE_SIZE_ID "p15, 1, %0, c0, c0, 0" macro

Completed in 5 milliseconds