Searched refs:XREG_CP15_CACHE_SIZE_SEL (Results 1 – 2 of 2) sorted by relevance
| /libcpu/arm/zynqmp-r5/ |
| A D | cache.c | 114 mtcp(XREG_CP15_CACHE_SIZE_SEL, 0); in Xil_DCacheInvalidate()
129 mtcp(XREG_CP15_CACHE_SIZE_SEL, 0); in Xil_DCacheInvalidateLine()
154 mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U); in Xil_DCacheInvalidateRange()
194 mtcp(XREG_CP15_CACHE_SIZE_SEL, 0); in Xil_DCacheFlush()
249 mtcp(XREG_CP15_CACHE_SIZE_SEL, 0); in Xil_DCacheFlushLine()
295 mtcp(XREG_CP15_CACHE_SIZE_SEL, 0); in Xil_DCacheStoreLine()
355 mtcp(XREG_CP15_CACHE_SIZE_SEL, 1); in Xil_ICacheInvalidate()
372 mtcp(XREG_CP15_CACHE_SIZE_SEL, 1); in Xil_ICacheInvalidateLine()
398 mtcp(XREG_CP15_CACHE_SIZE_SEL, 1U); in Xil_ICacheInvalidateRange()
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| A D | xreg_cortexr5.h | 210 #define XREG_CP15_CACHE_SIZE_SEL "p15, 2, %0, c0, c0, 0" macro
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