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Searched refs:XREG_CP15_CLEAN_DC_LINE_MVA_POC (Results 1 – 2 of 2) sorted by relevance

/libcpu/arm/zynqmp-r5/
A Dxreg_cortexr5.h277 #define XREG_CP15_CLEAN_DC_LINE_MVA_POC "p15, 0, %0, c7, c10, 1" macro
A Dcache.c296 mtcp(XREG_CP15_CLEAN_DC_LINE_MVA_POC, (adr & (~0x1F))); in Xil_DCacheStoreLine()

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