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Searched refs:XREG_CP15_CONTROL_C_BIT (Results 1 – 3 of 3) sorted by relevance

/libcpu/arm/zynqmp-r5/
A Dcache.c76 if ((CtrlReg & XREG_CP15_CONTROL_C_BIT) == 0x00000000U) in Xil_DCacheEnable()
82 CtrlReg |= (XREG_CP15_CONTROL_C_BIT); in Xil_DCacheEnable()
102 CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT); in Xil_DCacheDisable()
448 return CtrlReg & XREG_CP15_CONTROL_C_BIT; in rt_hw_cpu_dcache_status()
A Dxil_mpu.c215 if ((CtrlReg & XREG_CP15_CONTROL_C_BIT) != 0x00000000U) { in Xil_EnableMPU()
267 if ((CtrlReg & XREG_CP15_CONTROL_C_BIT) != 0x00000000U) { in Xil_DisableMPU()
A Dxreg_cortexr5.h231 #define XREG_CP15_CONTROL_C_BIT 0x00000004U macro

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