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Searched refs:XREG_CP15_CONTROL_I_BIT (Results 1 – 3 of 3) sorted by relevance

/libcpu/arm/zynqmp-r5/
A Dcache.c315 if ((CtrlReg & XREG_CP15_CONTROL_I_BIT) == 0x00000000U) in Xil_ICacheEnable()
321 CtrlReg |= (XREG_CP15_CONTROL_I_BIT); in Xil_ICacheEnable()
343 CtrlReg &= ~(XREG_CP15_CONTROL_I_BIT); in Xil_ICacheDisable()
437 return CtrlReg & XREG_CP15_CONTROL_I_BIT; in rt_hw_cpu_icache_status()
A Dxil_mpu.c218 if ((CtrlReg & XREG_CP15_CONTROL_I_BIT) != 0x00000000U) { in Xil_EnableMPU()
270 if ((CtrlReg & XREG_CP15_CONTROL_I_BIT) != 0x00000000U) { in Xil_DisableMPU()
A Dxreg_cortexr5.h227 #define XREG_CP15_CONTROL_I_BIT 0x00001000U macro

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