Searched refs:XREG_CP15_SYS_CONTROL (Results 1 – 3 of 3) sorted by relevance
| /libcpu/arm/zynqmp-r5/ |
| A D | cache.c | 72 CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); in Xil_DCacheEnable()
74 mfcp(XREG_CP15_SYS_CONTROL, CtrlReg); in Xil_DCacheEnable()
97 CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); in Xil_DCacheDisable()
99 mfcp(XREG_CP15_SYS_CONTROL, CtrlReg); in Xil_DCacheDisable()
104 mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); in Xil_DCacheDisable()
311 CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); in Xil_ICacheEnable()
313 mfcp(XREG_CP15_SYS_CONTROL, CtrlReg); in Xil_ICacheEnable()
340 mfcp(XREG_CP15_SYS_CONTROL, CtrlReg); in Xil_ICacheDisable()
345 mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); in Xil_ICacheDisable()
435 mfcp(XREG_CP15_SYS_CONTROL, CtrlReg); in rt_hw_cpu_icache_status()
[all …]
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| A D | xil_mpu.c | 211 CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); in Xil_EnableMPU()
213 mfcp(XREG_CP15_SYS_CONTROL,CtrlReg); in Xil_EnableMPU()
229 Reg = mfcp(XREG_CP15_SYS_CONTROL); in Xil_EnableMPU()
231 mfcp(XREG_CP15_SYS_CONTROL,Reg); in Xil_EnableMPU()
235 mtcp(XREG_CP15_SYS_CONTROL, Reg); in Xil_EnableMPU()
263 CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); in Xil_DisableMPU()
265 mfcp(XREG_CP15_SYS_CONTROL,CtrlReg); in Xil_DisableMPU()
283 Reg = mfcp(XREG_CP15_SYS_CONTROL); in Xil_DisableMPU()
285 mfcp(XREG_CP15_SYS_CONTROL,Reg); in Xil_DisableMPU()
289 mtcp(XREG_CP15_SYS_CONTROL, Reg); in Xil_DisableMPU()
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| A D | xreg_cortexr5.h | 213 #define XREG_CP15_SYS_CONTROL "p15, 0, %0, c1, c0, 0" macro
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