| /libcpu/mips/gs232/ |
| A D | cache_gcc.S | 78 lui a0, 0x8000
85 addu v0, $0, a0
86 addu v1, a0, a2
101 addu v0, $0, a0
102 addu v1, a0, a1
116 addu v0, $0, a0
117 addu v1, a0, a2
185 cache Index_Invalidate_I,0(a0)
186 cache Index_Invalidate_I,1(a0)
187 cache Index_Invalidate_I,2(a0)
[all …]
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| /libcpu/risc-v/common/ |
| A D | context_gcc.S | 36 csrw mstatus, a0
65 LOAD sp, (a0)
68 mv a0, a1
72 csrw mstatus, a0
143 andi a0, a0, 8
145 li a0, 0x80
187 mv a0, a2
208 move a0, a3
219 mv a0, sp
230 mv sp, a0
[all …]
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| A D | readme.md | 128 csrr a0, mcause
171 csrr a0, mscratch// 加载函数入口参数
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| A D | cpuport.c | 56 frame->a0 = (rt_ubase_t)parameter; in rt_hw_stack_init()
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| A D | interrupt_gcc.S | 118 csrr a0, mepc
119 STORE a0, 0 * REGBYTES(sp)
129 LOAD a0, 0 * REGBYTES(sp)
130 csrw mepc, a0
320 csrr a0, mcause
329 mv a0, s0
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| A D | rt_hw_stack_frame.h | 28 rt_ubase_t a0; /* x10 - a0 - return value or function argument 0 */ member
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| A D | trap_common.c | 96 rt_kprintf("a0 : 0x%08x\r\n", s_stack_frame->a0); in rt_show_stack_frame()
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| /libcpu/aarch64/common/include/ |
| A D | smccc.h | 18 unsigned long a0; member
35 void arm_smccc_smc(unsigned long a0, unsigned long a1, unsigned long a2,
40 void arm_smccc_hvc(unsigned long a0, unsigned long a1, unsigned long a2,
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| A D | hypercall.h | 28 return res.a0; in rt_hw_hypercall()
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| /libcpu/risc-v/common64/ |
| A D | syscall_c.c | 56 regs->a0, regs->a1, regs->a2, regs->a3, regs->a4, regs->a5, regs->a6); in syscall_handler()
57 regs->a0 = syscallfunc(regs->a0, regs->a1, regs->a2, regs->a3, regs->a4, regs->a5, regs->a6); in syscall_handler()
60 LOG_I("[0x%lx] %s ret: 0x%lx", rt_thread_self(), syscall_name, regs->a0); in syscall_handler()
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| A D | interrupt_gcc.S | 55 mv a0, t0
70 LOAD a0, 0(t0)
93 csrs sstatus, a0 /* restore to old csr */
98 csrrci a0, sstatus, 2 /* clear SIE */
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| A D | startup_gcc.S | 35 mv t1, a0 /* get hartid in S-mode frome a0 register */
102 beq a0, zero, 1f
106 sub x1, x1, a0
110 sub gp, gp, a0
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| A D | context_gcc.S | 78 LOAD sp, (a0)
81 mv s1, a0
101 STORE sp, (a0)
108 mv s1, a0
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| A D | cpuport_gcc.S | 18 LOAD a0, (sp) /* parameter */
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| A D | sbi.h | 150 register uintptr_t a0 __asm("a0") = (uintptr_t)(arg0); in sbi_call()
160 : "+r"(a0), "+r"(a1) \ in sbi_call()
164 ret.error = a0; in sbi_call()
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| A D | stack.h | 38 rt_ubase_t a0; /* x10 - a0 - return value or function argument 0 */ member
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| A D | trap.c | 54 rt_kprintf("\ta0(x10) = %p\ta1(x11) = %p\n", regs->a0, regs->a1); in dump_regs()
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| /libcpu/mips/common/ |
| A D | context_gcc.S | 32 REG_S sp, 0(a0) /* store sp in preempted tasks TCB */
43 REG_L sp, 0(a0) /* get new task stack pointer */
62 LONG_S a0, 0(t0)
87 move a0, k0
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| A D | stackframe.h | 199 mfc0 a0, CP0_STATUS
200 ori a0, STATMASK
201 xori a0, STATMASK
202 mtc0 a0, CP0_STATUS
204 and a0, v1, a0
208 or v0, a0
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| A D | mips.inc | 18 #define a0 $4 /* argument registers */
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| /libcpu/mips/pic32/ |
| A D | context_gcc.S | 41 mtc0 a0, CP0_STATUS
51 lw sp, 0(a0) /* get new task stack pointer */
65 sw sp, 0(a0) /* store sp in preempted tasks TCB */
86 sw a0, 0(t0)
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| /libcpu/risc-v/t-head/c908/ |
| A D | cache.c | 106 __asm__ volatile(OPC_DCACHE_CVAL1(a0):: in rt_hw_cpu_dcachel1_clean_local()
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| /libcpu/ti-dsp/c6x/ |
| A D | c66xx.h | 68 RT_REG_PAIR(a1, a0);
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| A D | stack.c | 99 thread_context->hw_register.a0 = 0xA00; in rt_hw_stack_init()
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| /libcpu/aarch64/common/ |
| A D | psci.c | 69 return res.a0; in psci_smc_call()
78 return res.a0; in psci_hvc_call()
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