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Searched refs:addr (Results 1 – 25 of 60) sorted by relevance

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/libcpu/ppc/ppc405/
A Dio.h13 static inline int in_8(const volatile unsigned char __iomem *addr) in in_8() argument
20 "isync" : "=r" (ret) : "m" (*addr)); in in_8()
29 extern inline int in_le16(const volatile unsigned short __iomem *addr) in in_le16() argument
36 "r" (addr), "m" (*addr)); in in_le16()
46 "isync" : "=r" (ret) : "m" (*addr)); in in_be16()
52 __asm__ __volatile__("sync; sthbrx %1,0,%2" : "=m" (*addr) : in out_le16()
53 "r" (val), "r" (addr)); in out_le16()
68 "r" (addr), "m" (*addr)); in in_le32()
78 "isync" : "=r" (ret) : "m" (*addr)); in in_be32()
84 __asm__ __volatile__("sync; stwbrx %1,0,%2" : "=m" (*addr) : in out_le32()
[all …]
/libcpu/mips/common/
A Dmips_cache.h105 #define cache_op(op, addr) \ argument
154 cache_op(HIT_INVALIDATE_I, addr); in flush_icache_line()
159 cache_op(FETCH_AND_LOCK_I, addr); in lock_icache_line()
164 cache_op(FETCH_AND_LOCK_D, addr); in lock_dcache_line()
174 cache_op(HIT_INVALIDATE_D, addr); in invalidate_dcache_line()
180 rt_ubase_t addr; in blast_dcache16() local
182 for (addr = start; addr < end; addr += g_mips_core.dcache_line_size) in blast_dcache16()
190 rt_ubase_t addr; in inv_dcache16() local
192 for (addr = start; addr < end; addr += g_mips_core.dcache_line_size) in inv_dcache16()
200 rt_ubase_t addr; in blast_icache16() local
[all …]
A Dmips_cache.c44 a = addr & ~(ic_lsize - 1); in r4k_icache_flush_range()
45 end = ((addr + size) - 1) & ~(ic_lsize - 1); in r4k_icache_flush_range()
61 a = addr & ~(ic_lsize - 1); in r4k_icache_lock_range()
62 end = ((addr + size) - 1) & ~(ic_lsize - 1); in r4k_icache_lock_range()
77 a = addr & ~(dc_lsize - 1); in r4k_dcache_inv()
78 end = ((addr + size) - 1) & ~(dc_lsize - 1); in r4k_dcache_inv()
100 a = addr & ~(dc_lsize - 1); in r4k_dcache_wback_inv()
101 end = ((addr + size) - 1) & ~(dc_lsize - 1); in r4k_dcache_wback_inv()
125 r4k_dcache_wback_inv(addr, size); in r4k_dma_cache_sync()
129 r4k_dcache_wback_inv(addr, size); in r4k_dma_cache_sync()
[all …]
A Dmips_addrspace.h159 #define REG8( addr ) (*(volatile u8 *) (addr)) argument
160 #define REG16( addr ) (*(volatile u16 *)(addr)) argument
161 #define REG32( addr ) (*(volatile u32 *)(addr)) argument
162 #define REG64( addr ) (*(volatile u64 *)(addr)) argument
/libcpu/aarch64/common/
A Dcache_ops.c31 void rt_hw_cpu_icache_invalidate(void *addr, rt_size_t size) in rt_hw_cpu_icache_invalidate() argument
33 __asm_invalidate_icache_range((rt_size_t)addr, (rt_size_t)addr + size); in rt_hw_cpu_icache_invalidate()
38 __asm_invalidate_dcache_range((rt_size_t)addr, (rt_size_t)addr + size); in rt_hw_cpu_dcache_invalidate()
41 void rt_hw_cpu_dcache_clean(void *addr, rt_size_t size) in rt_hw_cpu_dcache_clean() argument
43 __asm_flush_dcache_range((rt_size_t)addr, (rt_size_t)addr + size); in rt_hw_cpu_dcache_clean()
48 __asm_flush_dcache_range((rt_size_t)addr, (rt_size_t)addr + size); in rt_hw_cpu_dcache_clean_and_invalidate()
51 void rt_hw_cpu_icache_ops(int ops, void *addr, int size) in rt_hw_cpu_icache_ops() argument
55 rt_hw_cpu_icache_invalidate(addr, size); in rt_hw_cpu_icache_ops()
59 void rt_hw_cpu_dcache_ops(int ops, void *addr, int size) in rt_hw_cpu_dcache_ops() argument
63 rt_hw_cpu_dcache_clean(addr, size); in rt_hw_cpu_dcache_ops()
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/libcpu/risc-v/t-head/c908/
A Dcache.c82 icache_inv_range((unsigned long)addr, (unsigned long)((unsigned char *)addr + size)); in rt_hw_cpu_icache_invalidate_local()
88 dcache_inv_range((unsigned long)addr, (unsigned long)((unsigned char *)addr + size)); in rt_hw_cpu_dcache_invalidate_local()
92 void rt_hw_cpu_dcache_clean_local(void *addr, int size) in rt_hw_cpu_dcache_clean_local() argument
94 dcache_wb_range((unsigned long)addr, (unsigned long)((unsigned char *)addr + size)); in rt_hw_cpu_dcache_clean_local()
100 dcache_wbinv_range((unsigned long)addr, (unsigned long)((unsigned char *)addr + size)); in rt_hw_cpu_dcache_clean_invalidate_local()
120 rt_hw_cpu_icache_invalidate(addr, size); in rt_hw_cpu_icache_ops()
128 rt_hw_cpu_dcache_clean(addr, size); in rt_hw_cpu_dcache_ops()
132 rt_hw_cpu_dcache_invalidate(addr, size); in rt_hw_cpu_dcache_ops()
136 void rt_hw_sync_cache_local(void *addr, int size) in rt_hw_sync_cache_local() argument
138 rt_hw_cpu_dcachel1_clean_local(addr, size); in rt_hw_sync_cache_local()
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A Dcache.h51 void rt_hw_cpu_dcache_clean_local(void *addr, int size);
52 void rt_hw_cpu_dcache_invalidate_local(void *addr, int size);
53 void rt_hw_cpu_dcache_clean_invalidate_local(void *addr, int size);
55 void rt_hw_cpu_icache_invalidate_local(void *addr, int size);
96 void rt_hw_cpu_dcache_clean(void *addr, int size);
97 void rt_hw_cpu_dcache_invalidate(void *addr, int size);
98 void rt_hw_cpu_dcache_clean_invalidate(void *addr, int size);
104 void rt_hw_cpu_icache_invalidate(void *addr, int size);
125 void rt_hw_sync_cache_local(void *addr, int size);
/libcpu/risc-v/t-head/c906/
A Dcache.c77 icache_inv_range((unsigned long)addr, (unsigned long)((unsigned char *)addr + size)); in rt_hw_cpu_icache_invalidate_local()
83 dcache_inv_range((unsigned long)addr, (unsigned long)((unsigned char *)addr + size)); in rt_hw_cpu_dcache_invalidate_local()
87 void rt_hw_cpu_dcache_clean_local(void *addr, int size) in rt_hw_cpu_dcache_clean_local() argument
89 dcache_wb_range((unsigned long)addr, (unsigned long)((unsigned char *)addr + size)); in rt_hw_cpu_dcache_clean_local()
95 dcache_wbinv_range((unsigned long)addr, (unsigned long)((unsigned char *)addr + size)); in rt_hw_cpu_dcache_clean_and_invalidate_local()
109 rt_hw_cpu_icache_invalidate_local(addr, size); in rt_hw_cpu_icache_ops()
117 rt_hw_cpu_dcache_clean_local(addr, size); in rt_hw_cpu_dcache_ops()
121 rt_hw_cpu_dcache_invalidate_local(addr, size); in rt_hw_cpu_dcache_ops()
125 void rt_hw_sync_cache_local(void *addr, int size) in rt_hw_sync_cache_local() argument
127 rt_hw_cpu_dcache_clean_local(addr, size); in rt_hw_sync_cache_local()
[all …]
A Dcache.h32 void rt_hw_cpu_dcache_clean_local(void *addr, int size);
33 void rt_hw_cpu_dcache_invalidate_local(void *addr, int size);
34 void rt_hw_cpu_dcache_clean_and_invalidate_local(void *addr, int size);
36 void rt_hw_cpu_icache_invalidate_local(void *addr, int size);
77 void rt_hw_cpu_dcache_clean(void *addr, int size);
78 void rt_hw_cpu_dcache_invalidate(void *addr, int size);
79 void rt_hw_cpu_dcache_clean_and_invalidate(void *addr, int size);
85 void rt_hw_cpu_icache_invalidate(void *addr, int size);
106 void rt_hw_sync_cache_local(void *addr, int size);
/libcpu/mips/gs264/
A Dcache.c27 void rt_hw_cpu_icache_invalidate(void *addr, int size) in rt_hw_cpu_icache_invalidate() argument
30 rt_uint64_t start_addr = (rt_uint64_t)addr; in rt_hw_cpu_icache_invalidate()
34 void rt_hw_cpu_dcache_invalidate(void *addr, int size) in rt_hw_cpu_dcache_invalidate() argument
37 rt_uint64_t start_addr = (rt_uint64_t)addr; in rt_hw_cpu_dcache_invalidate()
41 void rt_hw_cpu_dcache_clean(void *addr, int size) in rt_hw_cpu_dcache_clean() argument
44 rt_uint64_t start_addr = (rt_uint64_t)addr; in rt_hw_cpu_dcache_clean()
48 void rt_hw_cpu_icache_ops(int ops, void *addr, int size) in rt_hw_cpu_icache_ops() argument
51 rt_hw_cpu_icache_invalidate(addr, size); in rt_hw_cpu_icache_ops()
54 void rt_hw_cpu_dcache_ops(int ops, void *addr, int size) in rt_hw_cpu_dcache_ops() argument
57 rt_hw_cpu_dcache_clean(addr, size); in rt_hw_cpu_dcache_ops()
[all …]
/libcpu/arm/cortex-a/
A Dcache.c27 void rt_hw_cpu_icache_invalidate(void *addr, int size) in rt_hw_cpu_icache_invalidate() argument
30 rt_uint32_t start_addr = (rt_uint32_t)addr; in rt_hw_cpu_icache_invalidate()
47 rt_uint32_t start_addr = (rt_uint32_t)addr; in rt_hw_cpu_dcache_invalidate()
64 rt_uint32_t start_addr = (rt_uint32_t)addr; in rt_hw_cpu_dcache_inv_range()
65 rt_uint32_t end_addr = (rt_uint32_t)addr + size; in rt_hw_cpu_dcache_inv_range()
92 void rt_hw_cpu_dcache_clean(void *addr, int size) in rt_hw_cpu_dcache_clean() argument
95 rt_uint32_t start_addr = (rt_uint32_t)addr; in rt_hw_cpu_dcache_clean()
112 rt_uint32_t start_addr = (rt_uint32_t)addr; in rt_hw_cpu_dcache_clean_and_invalidate()
131 rt_hw_cpu_icache_invalidate(addr, size); in rt_hw_cpu_icache_ops()
139 rt_hw_cpu_dcache_clean(addr, size); in rt_hw_cpu_dcache_ops()
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A Dcache.h14 void rt_hw_cpu_icache_invalidate(void *addr, int size);
15 void rt_hw_cpu_dcache_clean_and_invalidate(void *addr, int size);
A Dtrap.c138 uint32_t addr; in rt_hw_trap_undef() local
143 addr = regs->pc - 2; in rt_hw_trap_undef()
144 ins = (uint32_t)*(uint16_t *)addr; in rt_hw_trap_undef()
149 ins += *(uint16_t *)(addr + 2); in rt_hw_trap_undef()
154 addr = regs->pc - 4; in rt_hw_trap_undef()
155 ins = *(uint32_t *)addr; in rt_hw_trap_undef()
161 regs->pc = addr; in rt_hw_trap_undef()
/libcpu/arm/common/
A Dshowmem.c13 void rt_hw_show_memory(rt_uint32_t addr, rt_size_t size) in rt_hw_show_memory() argument
17 RT_ASSERT(addr); in rt_hw_show_memory()
19 addr = addr & ~0xF; in rt_hw_show_memory()
24 rt_kprintf("0x%08x: ", addr); in rt_hw_show_memory()
28 rt_kprintf("0x%08x ", *(rt_uint32_t *)addr); in rt_hw_show_memory()
30 addr += 4; in rt_hw_show_memory()
/libcpu/risc-v/virt64/
A Dcache.h20 rt_always_inline void rt_hw_cpu_dcache_clean_local(void *addr, int size) in rt_hw_cpu_dcache_clean_local() argument
22 RT_UNUSED(addr); in rt_hw_cpu_dcache_clean_local()
26 rt_always_inline void rt_hw_cpu_dcache_invalidate_local(void *addr, int size) in rt_hw_cpu_dcache_invalidate_local() argument
28 RT_UNUSED(addr); in rt_hw_cpu_dcache_invalidate_local()
32 rt_always_inline void rt_hw_cpu_dcache_clean_and_invalidate_local(void *addr, int size) in rt_hw_cpu_dcache_clean_and_invalidate_local() argument
34 RT_UNUSED(addr); in rt_hw_cpu_dcache_clean_and_invalidate_local()
50 rt_always_inline void rt_hw_cpu_icache_invalidate_local(void *addr, int size) in rt_hw_cpu_icache_invalidate_local() argument
52 RT_UNUSED(addr); in rt_hw_cpu_icache_invalidate_local()
86 void rt_hw_sync_cache_local(void *addr, int size);
A Dcache.c27 void rt_hw_cpu_icache_ops(int ops, void *addr, int size) in rt_hw_cpu_icache_ops() argument
31 rt_hw_cpu_icache_invalidate(addr, size); in rt_hw_cpu_icache_ops()
35 void rt_hw_cpu_dcache_ops(int ops, void *addr, int size) in rt_hw_cpu_dcache_ops() argument
39 rt_hw_cpu_dcache_clean(addr, size); in rt_hw_cpu_dcache_ops()
43 rt_hw_cpu_dcache_invalidate(addr, size); in rt_hw_cpu_dcache_ops()
57 void rt_hw_sync_cache_local(void *addr, int size) in rt_hw_sync_cache_local() argument
/libcpu/risc-v/common64/
A Dio.h25 static inline void writel(uint32_t val, volatile void *addr) in writel() argument
28 __arch_putl(val, addr); in writel()
31 static inline uint32_t readl(const volatile void *addr) in readl() argument
35 val = __arch_getl(addr); in readl()
41 uint32_t val, volatile void *addr, unsigned offset) in write_reg() argument
43 writel(val, (void *)((rt_size_t)addr + offset)); in write_reg()
47 const volatile void *addr, unsigned offset) in read_reg() argument
49 return readl((void *)((rt_size_t)addr + offset)); in read_reg()
A Driscv_io.h19 static inline void __raw_writeb(rt_uint8_t val, volatile void *addr) in __raw_writeb() argument
21 asm volatile("sb %0, 0(%1)" : : "r"(val), "r"(addr)); in __raw_writeb()
26 asm volatile("sh %0, 0(%1)" : : "r"(val), "r"(addr)); in __raw_writew()
31 asm volatile("sw %0, 0(%1)" : : "r"(val), "r"(addr)); in __raw_writel()
37 asm volatile("sd %0, 0(%1)" : : "r"(val), "r"(addr)); in __raw_writeq()
41 static inline rt_uint8_t __raw_readb(const volatile void *addr) in __raw_readb() argument
45 asm volatile("lb %0, 0(%1)" : "=r"(val) : "r"(addr)); in __raw_readb()
49 static inline rt_uint16_t __raw_readw(const volatile void *addr) in __raw_readw() argument
53 asm volatile("lh %0, 0(%1)" : "=r"(val) : "r"(addr)); in __raw_readw()
61 asm volatile("lw %0, 0(%1)" : "=r"(val) : "r"(addr)); in __raw_readl()
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A Dmmu.h38 #define GET_PF_ID(addr) ((addr) >> PAGE_OFFSET_BIT) argument
39 #define GET_PF_OFFSET(addr) __MASKVALUE(addr, PAGE_OFFSET_MASK) argument
40 #define GET_L1(addr) __PARTBIT(addr, VPN2_SHIFT, VPN2_BIT) argument
41 #define GET_L2(addr) __PARTBIT(addr, VPN1_SHIFT, VPN1_BIT) argument
42 #define GET_L3(addr) __PARTBIT(addr, VPN0_SHIFT, VPN0_BIT) argument
/libcpu/mips/gs232/
A Dcpuport.c46 unsigned long addr = start_addr & ~(lsize - 1); in flush_cache() local
50 cache_op(Hit_Writeback_Inv_D, addr); in flush_cache()
51 cache_op(Hit_Invalidate_I, addr); in flush_cache()
52 if (addr == aend) in flush_cache()
54 addr += lsize; in flush_cache()
/libcpu/arm/cortex-m7/
A Dcpu_cache.c37 void rt_hw_cpu_icache_ops(int ops, void* addr, int size) in rt_hw_cpu_icache_ops() argument
39 rt_uint32_t address = (rt_uint32_t)addr & (rt_uint32_t) ~(L1CACHE_LINESIZE_BYTE - 1); in rt_hw_cpu_icache_ops()
40 rt_int32_t size_byte = size + address - (rt_uint32_t)addr; in rt_hw_cpu_icache_ops()
71 void rt_hw_cpu_dcache_ops(int ops, void* addr, int size) in rt_hw_cpu_dcache_ops() argument
73 rt_uint32_t startAddr = (rt_uint32_t)addr & (rt_uint32_t)~(L1CACHE_LINESIZE_BYTE - 1); in rt_hw_cpu_dcache_ops()
74 rt_uint32_t size_byte = size + (rt_uint32_t)addr - startAddr; in rt_hw_cpu_dcache_ops()
/libcpu/c-sky/common/
A Dcsi_instr.h346 __ALWAYS_INLINE uint8_t __LDRBT(volatile uint8_t *addr) in __LDRBT() argument
350 __ASM volatile("ldb %0, (%1, 0)" : "=r"(result) : "r"(addr)); in __LDRBT()
361 __ALWAYS_INLINE uint16_t __LDRHT(volatile uint16_t *addr) in __LDRHT() argument
366 __ASM volatile("ldh %0, (%1, 0)" : "=r"(result) : "r"(addr)); in __LDRHT()
377 __ALWAYS_INLINE uint32_t __LDRT(volatile uint32_t *addr) in __LDRT() argument
382 __ASM volatile("ldw %0, (%1, 0)" : "=r"(result) : "r"(addr)); in __LDRT()
393 __ALWAYS_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr) in __STRBT() argument
396 __ASM volatile("stb %1, (%0, 0)" :: "r"(addr), "r"((uint32_t)value) : "memory"); in __STRBT()
406 __ALWAYS_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr) in __STRHT() argument
419 __ALWAYS_INLINE void __STRT(uint32_t value, volatile uint32_t *addr) in __STRT() argument
[all …]
A Dcsi_core.h173 void drv_dcache_invalid_range(uint32_t *addr, int32_t dsize);
181 void drv_dcache_clean_range(uint32_t *addr, int32_t dsize);
189 void drv_dcache_clean_invalid_range(uint32_t *addr, int32_t dsize);
/libcpu/aarch64/common/include/
A Dcache.h21 void rt_hw_cpu_dcache_clean(void *addr, unsigned long size);
36 void rt_hw_cpu_icache_invalidate(void *addr, rt_size_t size);
37 void rt_hw_cpu_dcache_clean_and_invalidate(void *addr, rt_size_t size);
A Dtlb.h19 #define TLBI_ARG(addr, asid) \ argument
21 rt_ubase_t arg = (rt_ubase_t)(addr) >> ARCH_PAGE_SHIFT; \

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