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Searched refs:base (Results 1 – 7 of 7) sorted by relevance

/libcpu/arm/am335x/
A Dam33xx.h93 #define CM_PER(base) ((base) + 0) argument
206 #define DMTIMER_TIDR(base) REG32(base + 0x0) argument
207 #define DMTIMER_TIOCP_CFG(base) REG32(base + 0x10) argument
208 #define DMTIMER_IRQ_EOI(base) REG32(base + 0x20) argument
209 #define DMTIMER_IRQSTATUS_RAW(base) REG32(base + 0x24) argument
210 #define DMTIMER_IRQSTATUS(base) REG32(base + 0x28) argument
211 #define DMTIMER_IRQENABLE_SET(base) REG32(base + 0x2C) argument
212 #define DMTIMER_IRQENABLE_CLR(base) REG32(base + 0x30) argument
213 #define DMTIMER_IRQWAKEEN(base) REG32(base + 0x34) argument
214 #define DMTIMER_TCLR(base) REG32(base + 0x38) argument
[all …]
/libcpu/ppc/ppc405/
A Dstart_gcc.S36 #define SAVE_GPR(n, base) stw n,GPR0+4*(n)(base) argument
37 #define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base) argument
38 #define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base) argument
39 #define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base) argument
40 #define SAVE_10GPRS(n,base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base) argument
41 #define REST_GPR(n, base) lwz n,GPR0+4*(n)(base) argument
42 #define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base) argument
43 #define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base) argument
44 #define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base) argument
45 #define REST_10GPRS(n,base) REST_8GPRS(n, base); REST_2GPRS(n+8, base) argument
/libcpu/arm/cortex-r52/
A Dgicv3.c427 rt_uint32_t base; in arm_gicv3_wait_rwp() local
441 base = _gic_table[index].dist_hw_base; in arm_gicv3_wait_rwp()
445 while (__REG32(base) & rwp_bit) in arm_gicv3_wait_rwp()
552 rt_uint32_t base; in arm_gic_redist_init() local
558 base = _gic_table[index].redist_hw_base[cpu_id]; in arm_gic_redist_init()
561 GIC_RDIST_WAKER(base) &= ~(1U << 1); in arm_gic_redist_init()
563 while (GIC_RDIST_WAKER(base) & (1 << 2)) in arm_gic_redist_init()
569 GIC_RDISTSGI_ICENABLER0(base) = 0xFFFFFFFF; in arm_gic_redist_init()
573 GIC_RDISTSGI_ICPENDR0(base) = 0xFFFFFFFF; in arm_gic_redist_init()
576 GIC_RDISTSGI_IGROUPR0(base, 0) = 0xFFFFFFFF; in arm_gic_redist_init()
[all …]
/libcpu/arm/cortex-a/
A Dgicv3.c461 rt_uint32_t base; in arm_gicv3_wait_rwp() local
475 base = _gic_table[index].dist_hw_base; in arm_gicv3_wait_rwp()
479 while (__REG32(base) & rwp_bit) in arm_gicv3_wait_rwp()
586 rt_uint32_t base; in arm_gic_redist_init() local
592 base = _gic_table[index].redist_hw_base[cpu_id]; in arm_gic_redist_init()
594 GIC_RDIST_WAKER(base) &= ~(1U << 1); in arm_gic_redist_init()
595 while (GIC_RDIST_WAKER(base) & (1 << 2)) in arm_gic_redist_init()
601 GIC_RDISTSGI_ICENABLER0(base) = 0xFFFFFFFF; in arm_gic_redist_init()
605 GIC_RDISTSGI_ICPENDR0(base) = 0xFFFFFFFF; in arm_gic_redist_init()
608 GIC_RDISTSGI_IGROUPR0(base, 0) = 0xFFFFFFFF; in arm_gic_redist_init()
[all …]
/libcpu/mips/common/
A Dmips_cache.h115 #define cache16_unroll32(base, op) \ argument
138 : "r" (base), \
/libcpu/aarch64/common/
A Dmmu.c700 rt_ubase_t base; in rt_ioremap_early() local
716 base = (rt_ubase_t)paddr & (~ARCH_SECTION_MASK); in rt_ioremap_early()
720 if (_map_single_page_2M(tbl, base, base, MMU_MAP_K_DEVICE, RT_TRUE)) in rt_ioremap_early()
725 base += ARCH_SECTION_SIZE; in rt_ioremap_early()
A Dgicv3.c561 rt_uint64_t base; in arm_gicv3_wait_rwp() local
569 base = _gic_table[index].redist_hw_base[cpu_id]; in arm_gicv3_wait_rwp()
574 base = _gic_table[index].dist_hw_base; in arm_gicv3_wait_rwp()
578 while (HWREG32(base) & rwp_bit) in arm_gicv3_wait_rwp()

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