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Searched refs:bit (Results 1 – 25 of 33) sorted by relevance

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/libcpu/risc-v/common64/
A Driscv.h18 #define __SIZE(bit) (1ULL << (bit)) argument
19 #define __MASK(bit) (__SIZE(bit) - 1ULL) argument
21 #define __UMASK(bit) (~(__MASK(bit))) argument
29 #define __ALIGNUP(value,bit) (((value) + __MASK(bit)) & __UMASK(bit)) argument
30 #define __ALIGNDOWN(value,bit) ((value) & __UMASK(bit)) argument
A Dencoding.h220 #define set_csr(reg, bit) ({ unsigned long __tmp; \ argument
221 if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
222 asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
224 asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
227 #define clear_csr(reg, bit) ({ unsigned long __tmp; \ argument
228 if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
229 asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
231 asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
/libcpu/risc-v/common/
A Driscv-ops.h26 #define set_csr(reg, bit) ({ unsigned long __tmp; \ argument
27 if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
28 asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
30 asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
33 #define clear_csr(reg, bit) ({ unsigned long __tmp; \ argument
34 if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
35 asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
37 asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
/libcpu/arm/am335x/
A Dcpu.c38 rt_inline void cache_enable(rt_uint32_t bit) in cache_enable() argument
45 orr value, value, bit in cache_enable()
50 rt_inline void cache_disable(rt_uint32_t bit) in cache_disable() argument
57 bic value, value, bit in cache_disable()
70 rt_inline void cache_enable(rt_uint32_t bit) in cache_enable() argument
77 :"r" (bit) \ in cache_enable()
81 rt_inline void cache_disable(rt_uint32_t bit) in cache_disable() argument
88 :"r" (bit) \ in cache_disable()
100 rt_inline void cache_enable(rt_uint32_t bit) in cache_enable() argument
109 :"r"(bit) \ in cache_enable()
[all …]
A Dstart_iar.s17 I_Bit DEFINE 0x80 ; when I bit is set, IRQ is disabled
18 F_Bit DEFINE 0x40 ; when F bit is set, FIQ is disabled
A Dcp15_gcc.S114 mcr p15, #0, r0, c1, c0, #0 @ clear mmu bit
122 mcr p15, #0, r0, c1, c0, #0 @ set mmu enable bit
A Dcp15_iar.s121 MCR p15, #0, r0, c1, c0, #0 ; clear mmu bit
129 MCR p15, #0, r0, c1, c0, #0 ; set mmu enable bit
A Dstart_gcc.S19 .equ I_Bit, 0x80 @ when I bit is set, IRQ is disabled
20 .equ F_Bit, 0x40 @ when F bit is set, FIQ is disabled
/libcpu/arm/s3c24x0/
A Dcpu.c32 rt_inline void cache_enable(rt_uint32_t bit) in cache_enable() argument
39 :"r" (bit) \ in cache_enable()
43 rt_inline void cache_disable(rt_uint32_t bit) in cache_disable() argument
50 :"r" (bit) \ in cache_disable()
68 rt_inline void cache_enable(rt_uint32_t bit) in cache_enable() argument
75 orr value, value, bit in cache_enable()
80 rt_inline void cache_disable(rt_uint32_t bit) in cache_disable() argument
87 bic value, value, bit in cache_disable()
A Ds3c24x0.h562 #define ClearPending(bit) {SRCPND = bit;INTPND = bit;INTPND;} argument
/libcpu/arm/arm926/
A Dcpuport.c30 rt_inline void cache_enable(rt_uint32_t bit) in cache_enable() argument
37 : "r"(bit) \ in cache_enable()
41 rt_inline void cache_disable(rt_uint32_t bit) in cache_disable() argument
48 : "r"(bit) \ in cache_disable()
66 rt_inline void cache_enable(rt_uint32_t bit) in cache_enable() argument
73 orr value, value, bit in cache_enable()
78 rt_inline void cache_disable(rt_uint32_t bit) in cache_disable() argument
85 bic value, value, bit in cache_disable()
/libcpu/arm/dm36x/
A Dcpuport.c29 rt_inline void cache_enable(rt_uint32_t bit) in cache_enable() argument
36 :"r" (bit) \ in cache_enable()
40 rt_inline void cache_disable(rt_uint32_t bit) in cache_disable() argument
47 :"r" (bit) \ in cache_disable()
65 rt_inline void cache_enable(rt_uint32_t bit) in cache_enable() argument
72 orr value, value, bit in cache_enable()
77 rt_inline void cache_disable(rt_uint32_t bit) in cache_disable() argument
84 bic value, value, bit in cache_disable()
/libcpu/arm/armv6/
A Dcpuport.c29 rt_inline void cache_enable(rt_uint32_t bit) in cache_enable() argument
36 :"r" (bit) \ in cache_enable()
40 rt_inline void cache_disable(rt_uint32_t bit) in cache_disable() argument
47 :"r" (bit) \ in cache_disable()
67 rt_inline void cache_enable(rt_uint32_t bit) in cache_enable() argument
74 orr value, value, bit in cache_enable()
79 rt_inline void cache_disable(rt_uint32_t bit) in cache_disable() argument
86 bic value, value, bit in cache_disable()
A Darm_entry_gcc.S101 tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC instruction has bit 27
102 tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2 instruction
/libcpu/ppc/ppc405/include/asm/
A Dppc4xx.h37 #define PPC_REG_VAL(bit, value) ((value) << ((PPC_REG_BITS - 1) - (bit))) argument
/libcpu/arm/lpc214x/
A Dcontext_rvds.S20 I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled
21 F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled
A Dstart_rvds.S47 I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled
48 F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled
/libcpu/arm/realview-a8-vmm/
A Dcp15_gcc.S109 mcr p15, #0, r0, c1, c0, #0 @ clear mmu bit
117 mcr p15, #0, r0, c1, c0, #0 @ set mmu enable bit
A Dstart_gcc.S21 .equ I_Bit, 0x80 @ when I bit is set, IRQ is disabled
22 .equ F_Bit, 0x40 @ when F bit is set, FIQ is disabled
/libcpu/arm/cortex-a/
A Dcp15_gcc.S122 mcr p15, #0, r0, c1, c0, #0 @ clear mmu bit
130 mcr p15, #0, r0, c1, c0, #0 @ set mmu enable bit
/libcpu/arm/sep4020/
A Dstart_rvds.S43 I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled
44 F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled
193 MSR cpsr_c, R4 ;SYSTEM mode, @32-bit code mode
196 MOV R4, #0XD3 ;chmod to svc modle, CPSR IRQ bit is disable
/libcpu/risc-v/rv64/
A Dencoding.h203 #define set_csr(reg, bit) ({ unsigned long __tmp; \ argument
204 if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
205 asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
207 asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
210 #define clear_csr(reg, bit) ({ unsigned long __tmp; \ argument
211 if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
212 asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
214 asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
/libcpu/ti-dsp/c28x/
A Dcontext.s59 #error RTOS bit (0x8000) must not be set in ZERO_LATENCY_INT_MASK
336 ; CSB will return the number of 0's minus 1 above the highest set bit.
/libcpu/arm/cortex-r52/
A Dcp15_gcc.S60 mov r3, r3, lsr #23 @ left align loc bit field
76 clz r5, r4 @ find bit position of way size increment
/libcpu/arm/zynqmp-r5/
A Dstart_gcc.S22 .equ I_Bit, 0x80 @ when I bit is set, IRQ is disabled
23 .equ F_Bit, 0x40 @ when F bit is set, FIQ is disabled

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