1 /*
2  * Copyright (c) 2020, Shenzhen Academy of Aerospace Technology
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  *
6  * Change Logs:
7  * Date           Author       Notes
8  * 2020-10-16     Dystopia     the first version
9  */
10 
11 #ifndef __BM3803_H__
12 #define __BM3803_H__
13 
14 struct lregs
15 {
16     /* address = 0x80000000 */
17     unsigned int memcfg1;           /* 0x00 */
18     unsigned int memcfg2;
19     unsigned int memcfg3;
20     unsigned int failaddr;
21 
22     unsigned int memstatus;     /* 0x10 */
23     unsigned int cachectrl;
24     unsigned int powerdown;
25     unsigned int writeprot1;
26 
27     unsigned int writeprot2;        /* 0x20 */
28     unsigned int pcr;
29     unsigned int dummy2;
30     unsigned int dummy3;
31 
32     unsigned int dummy4;            /* 0x30 */
33     unsigned int dummy5;
34     unsigned int dummy6;
35     unsigned int dummy7;
36 
37     unsigned int timercnt1;     /* 0x40 */
38     unsigned int timerload1;
39     unsigned int timerctrl1;
40     unsigned int wdog;
41 
42     unsigned int timercnt2;        /* 0x50 */
43     unsigned int timerload2;
44     unsigned int timerctrl2;
45     unsigned int dummy8;
46 
47     unsigned int scalercnt;        /* 0x60 */
48     unsigned int scalerload;
49     unsigned int dummy9;
50     unsigned int dummy10;
51 
52     unsigned int uartdata1;        /* 0x70 */
53     unsigned int uartstatus1;
54     unsigned int uartctrl1;
55     unsigned int uartscaler1;
56 
57     unsigned int uartdata2;        /* 0x80 */
58     unsigned int uartstatus2;
59     unsigned int uartctrl2;
60     unsigned int uartscaler2;
61 
62     unsigned int irqmask;           /* 0x90 */
63     unsigned int irqpend;
64     unsigned int irqforce;
65     unsigned int irqclear;
66 
67     unsigned int piodata;            /* 0xA0 */
68     unsigned int piodir;
69     unsigned int pioirq;
70     unsigned int dummy11;
71 
72     unsigned int imask2;            /* 0xB0 */
73     unsigned int ipend2;
74     unsigned int istat2;
75     unsigned int dummy12;
76 
77     unsigned int dummy13;          /* 0xC0 */
78     unsigned int dcomstatus;
79     unsigned int dcomctrl;
80     unsigned int dcomscaler;
81 
82     unsigned int dummy14;           /* 0xD0 */
83     unsigned int dummy15;
84     unsigned int dummy16;
85     unsigned int dummy17;
86 
87     unsigned int uartdata3;         /* 0xE0 */
88     unsigned int uartstatus3;
89     unsigned int uartctrl3;
90     unsigned int uartscaler3;
91 };
92 
93 #define PREGS 0x80000000
94 
95 #define UART1_BASE (PREGS + 0x70)
96 
97 #define TIMER2_TT 0x19
98 #define UART1_TT 0x13
99 
100 #endif
101