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Searched refs:exception (Results 1 – 16 of 16) sorted by relevance

/libcpu/arm/cortex-m3/
A Dcontext_iar.S23 NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception
75 LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch)
142 ; set the PendSV and SysTick exception priority
149 LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch)
164 ; ensure PendSV exception taken place before subsequent operation
A Dcontext_rvds.S22 NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception
77 LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch)
148 ; set the PendSV and SysTick exception priority
155 ; trigger the PendSV exception (causes context switch)
170 ; ensure PendSV exception taken place before subsequent operation
/libcpu/risc-v/common/
A Dtrap_common.c73 rt_uint32_t exception = !(mcause & 0x80000000); in rt_rv32_system_irq_handler() local
74 if(exception) in rt_rv32_system_irq_handler()
/libcpu/arm/cortex-m0/
A Dcontext_iar.S23 NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception
75 LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch)
166 ; set the PendSV and SysTick exception priority
173 ; trigger the PendSV exception (causes context switch)
189 ; ensure PendSV exception taken place before subsequent operation
A Dcontext_rvds.S23 NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception
78 LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch)
171 ; set the PendSV and SysTick exception priority
178 ; trigger the PendSV exception (causes context switch)
192 ; ensure PendSV exception taken place before subsequent operation
/libcpu/arm/cortex-m23/
A Dcontext_iar.S24 NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception
76 LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch)
167 ; set the PendSV and SysTick exception priority
174 ; trigger the PendSV exception (causes context switch)
190 ; ensure PendSV exception taken place before subsequent operation
A Dcontext_rvds.S24 NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception
79 LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch)
172 ; set the PendSV and SysTick exception priority
179 ; trigger the PendSV exception (causes context switch)
193 ; ensure PendSV exception taken place before subsequent operation
/libcpu/arm/cortex-m7/
A Dcontext_iar.S25 NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception
77 LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch)
189 ; set the PendSV and SysTick exception priority
196 LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch)
211 ; ensure PendSV exception taken place before subsequent operation
A Dcontext_rvds.S24 NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception
79 LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch)
189 ; set the PendSV and SysTick exception priority
196 ; trigger the PendSV exception (causes context switch)
211 ; ensure PendSV exception taken place before subsequent operation
/libcpu/arm/cortex-m4/
A Dcontext_iar.S26 NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception
80 LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch)
192 ; set the PendSV and SysTick exception priority
199 LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch)
218 ; ensure PendSV exception taken place before subsequent operation
A Dcontext_rvds.S25 NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception
80 LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch)
190 ; set the PendSV and SysTick exception priority
197 ; trigger the PendSV exception (causes context switch)
216 ; ensure PendSV exception taken place before subsequent operation
A DREADME.md50 …on/107706/0100/Exceptions-and-interrupts-overview/Special-registers-for-exception-masking/BASEPRI)…
53 …on/107706/0100/Exceptions-and-interrupts-overview/Special-registers-for-exception-masking/BASEPRI)…
/libcpu/arm/cortex-m33/
A Dcontext_iar.S25 NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception
80 LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch)
234 ; set the PendSV and SysTick exception priority
241 LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch)
256 ; ensure PendSV exception taken place before subsequent operation
A Dcontext_rvds.S24 NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception
82 LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch)
235 ; set the PendSV and SysTick exception priority
242 ; trigger the PendSV exception (causes context switch)
257 ; ensure PendSV exception taken place before subsequent operation
/libcpu/avr32/uc3/
A Dexception_gcc.S56 .section .exception, "ax", @progbits
/libcpu/ti-dsp/c6x/
A Dintexc.asm134 ; return from trap restore exception context

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