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/libcpu/aarch64/common/include/
A Dgic.h17 int arm_gic_get_active_irq(rt_uint64_t index);
18 void arm_gic_ack(rt_uint64_t index, int irq);
20 void arm_gic_mask(rt_uint64_t index, int irq);
21 void arm_gic_umask(rt_uint64_t index, int irq);
24 void arm_gic_set_pending_irq(rt_uint64_t index, int irq);
25 void arm_gic_clear_pending_irq(rt_uint64_t index, int irq);
30 void arm_gic_clear_active(rt_uint64_t index, int irq);
42 rt_uint64_t arm_gic_get_binary_point(rt_uint64_t index);
50 rt_uint64_t arm_gic_get_interface_id(rt_uint64_t index);
58 void arm_gic_dump_type(rt_uint64_t index);
[all …]
A Dgicv3.h143 int arm_gic_get_active_irq(rt_uint64_t index);
144 void arm_gic_ack(rt_uint64_t index, int irq);
146 void arm_gic_mask(rt_uint64_t index, int irq);
147 void arm_gic_umask(rt_uint64_t index, int irq);
150 void arm_gic_set_pending_irq(rt_uint64_t index, int irq);
156 void arm_gic_clear_active(rt_uint64_t index, int irq);
169 rt_uint64_t arm_gic_get_binary_point(rt_uint64_t index);
179 rt_uint64_t arm_gic_get_interface_id(rt_uint64_t index);
182 rt_uint64_t arm_gic_get_group(rt_uint64_t index, int irq);
192 void arm_gic_dump_type(rt_uint64_t index);
[all …]
/libcpu/arm/cortex-a/
A Dgic.h17 int arm_gic_get_active_irq(rt_uint32_t index);
18 void arm_gic_ack(rt_uint32_t index, int irq);
20 void arm_gic_mask(rt_uint32_t index, int irq);
21 void arm_gic_umask(rt_uint32_t index, int irq);
24 void arm_gic_set_pending_irq(rt_uint32_t index, int irq);
25 void arm_gic_clear_pending_irq(rt_uint32_t index, int irq);
30 void arm_gic_clear_active(rt_uint32_t index, int irq);
42 rt_uint32_t arm_gic_get_binary_point(rt_uint32_t index);
50 rt_uint32_t arm_gic_get_interface_id(rt_uint32_t index);
58 void arm_gic_dump_type(rt_uint32_t index);
[all …]
A Dgic.c67 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_get_active_irq()
70 irq += _gic_table[index].offset; in arm_gic_get_active_irq()
78 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_ack()
91 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_mask()
103 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_umask()
115 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_get_pending_irq()
144 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_set_pending_irq()
165 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_clear_pending_irq()
187 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_set_configuration()
203 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_get_configuration()
[all …]
A Dgicv3.c59 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_get_active_irq()
69 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_ack()
81 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_mask()
102 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_umask()
123 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_get_pending_irq()
152 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_set_pending_irq()
173 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_clear_pending_irq()
195 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_set_configuration()
347 index = index; in arm_gic_set_binary_point()
357 index = index; in arm_gic_get_binary_point()
[all …]
A Dgicv3.h144 int arm_gic_get_active_irq(rt_uint32_t index);
145 void arm_gic_ack(rt_uint32_t index, int irq);
147 void arm_gic_mask(rt_uint32_t index, int irq);
148 void arm_gic_umask(rt_uint32_t index, int irq);
157 void arm_gic_clear_active(rt_uint32_t index, int irq);
169 rt_uint32_t arm_gic_get_binary_point(rt_uint32_t index);
176 rt_uint32_t arm_gic_get_interface_id(rt_uint32_t index);
184 int arm_gic_cpu_init(rt_uint32_t index);
185 int arm_gic_redist_init(rt_uint32_t index);
187 void arm_gic_dump_type(rt_uint32_t index);
[all …]
/libcpu/arm/cortex-r52/
A Dgicv3.c59 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_get_active_irq()
69 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_ack()
80 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_mask()
101 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_umask()
122 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_get_pending_irq()
151 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_set_pending_irq()
172 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_clear_pending_irq()
194 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_set_configuration()
347 index = index; in arm_gic_set_binary_point()
357 index = index; in arm_gic_get_binary_point()
[all …]
A Dgicv3.h144 int arm_gic_get_active_irq(rt_uint32_t index);
145 void arm_gic_ack(rt_uint32_t index, int irq);
147 void arm_gic_mask(rt_uint32_t index, int irq);
148 void arm_gic_umask(rt_uint32_t index, int irq);
157 void arm_gic_clear_active(rt_uint32_t index, int irq);
169 rt_uint32_t arm_gic_get_binary_point(rt_uint32_t index);
175 rt_uint32_t arm_gic_get_interface_id(rt_uint32_t index);
183 int arm_gic_cpu_init(rt_uint32_t index);
184 int arm_gic_redist_init(rt_uint32_t index);
186 void arm_gic_dump_type(rt_uint32_t index);
[all …]
/libcpu/aarch64/common/
A Dgic.c69 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_get_active_irq()
72 irq += _gic_table[index].offset; in arm_gic_get_active_irq()
80 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_ack()
93 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_mask()
105 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_umask()
117 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_get_pending_irq()
146 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_set_pending_irq()
167 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_clear_pending_irq()
189 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_set_configuration()
205 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_get_configuration()
[all …]
A Dgicv3.c52 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_get_active_irq()
62 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_ack()
73 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_mask()
94 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_umask()
115 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_get_pending_irq()
144 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_set_pending_irq()
165 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_clear_pending_irq()
187 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_set_configuration()
356 RT_UNUSED(index); in arm_gic_set_binary_point()
366 RT_UNUSED(index); in arm_gic_get_binary_point()
[all …]
A Dinterrupt.c58 rt_uint32_t index; in rt_hw_interrupt_init() local
69 for (index = 0; index < MAX_HANDLERS; index ++) in rt_hw_interrupt_init()
71 isr_table[index].handler = default_isr_handler; in rt_hw_interrupt_init()
72 isr_table[index].param = RT_NULL; in rt_hw_interrupt_init()
74 rt_strncpy(isr_table[index].name, "unknown", RT_NAME_MAX); in rt_hw_interrupt_init()
75 isr_table[index].counter = 0; in rt_hw_interrupt_init()
/libcpu/arm/realview-a8-vmm/
A Dgic.c57 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_get_active_irq()
60 irq += _gic_table[index].offset; in arm_gic_get_active_irq()
68 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_ack()
82 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_mask()
94 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_clear_pending()
106 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_clear_active()
118 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_set_cpu()
135 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_umask()
156 void arm_gic_dump(rt_uint32_t index) in arm_gic_dump() argument
195 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_dist_init()
[all …]
A Dgic.h14 int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start);
15 int arm_gic_cpu_init(rt_uint32_t index, rt_uint32_t cpu_base);
17 void arm_gic_mask(rt_uint32_t index, int irq);
18 void arm_gic_umask(rt_uint32_t index, int irq);
19 void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask);
20 void arm_gic_set_group(rt_uint32_t index, int vector, int group);
22 int arm_gic_get_active_irq(rt_uint32_t index);
23 void arm_gic_ack(rt_uint32_t index, int irq);
25 void arm_gic_trigger(rt_uint32_t index, int target_cpu, int irq);
26 void arm_gic_clear_sgi(rt_uint32_t index, int target_cpu, int irq);
[all …]
/libcpu/arm/zynqmp-r5/
A Dgic.c56 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_get_active_irq()
59 irq += _gic_table[index].offset; in arm_gic_get_active_irq()
67 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_ack()
69 irq = irq - _gic_table[index].offset; in arm_gic_ack()
81 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_mask()
83 irq = irq - _gic_table[index].offset; in arm_gic_mask()
93 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_set_cpu()
95 irq = irq - _gic_table[index].offset; in arm_gic_set_cpu()
110 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_umask()
136 RT_ASSERT(index < ARM_GIC_MAX_NR); in arm_gic_dist_init()
[all …]
A Dgic.h14 int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start);
15 int arm_gic_cpu_init(rt_uint32_t index, rt_uint32_t cpu_base);
17 void arm_gic_mask(rt_uint32_t index, int irq);
18 void arm_gic_umask(rt_uint32_t index, int irq);
19 void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask);
21 int arm_gic_get_active_irq(rt_uint32_t index);
22 void arm_gic_ack(rt_uint32_t index, int irq);
24 void arm_gic_trigger(rt_uint32_t index, int target_cpu, int irq);
25 void arm_gic_clear_sgi(rt_uint32_t index, int target_cpu, int irq);
27 void arm_gic_dump_type(rt_uint32_t index);
/libcpu/arm/cortex-m33/
A Dmpu.c55 rt_uint8_t index; in _mpu_rbar_rlar() local
67 for (index = 0U; index < 8U; index++) in _mpu_rbar_rlar()
83 if (index == 8U) in _mpu_rbar_rlar()
129 rt_uint8_t index; in rt_hw_mpu_init() local
154 for (index = 0U; index < 8U; index++) in rt_hw_mpu_init()
160 for (index = 0U; index < NUM_STATIC_REGIONS; index++) in rt_hw_mpu_init()
171 ARM_MPU_SetRegion(index, static_regions[index].attr.rbar, static_regions[index].attr.rlar); in rt_hw_mpu_init()
181 rt_uint8_t index; in rt_hw_mpu_add_region() local
218 rt_uint8_t index; in rt_hw_mpu_delete_region() local
239 rt_uint8_t index; in rt_hw_mpu_update_region() local
[all …]
/libcpu/arm/AT91SAM7X/
A Dinterrupt.c41 rt_base_t index; in rt_hw_interrupt_init() local
44 for(index=0; index < MAX_HANDLERS; index++) in rt_hw_interrupt_init()
46 irq_desc[index].handler = (rt_isr_handler_t)rt_hw_interrupt_handler; in rt_hw_interrupt_init()
47 irq_desc[index].param = RT_NULL; in rt_hw_interrupt_init()
50 for (index = 0; index < MAX_HANDLERS; index ++) in rt_hw_interrupt_init()
52 AT91C_BASE_AIC->AIC_SVR[index] = (rt_uint32_t)rt_hw_interrupt_handler; in rt_hw_interrupt_init()
/libcpu/arm/cortex-m7/
A Dmpu.c92 rt_uint8_t index; in rt_hw_mpu_init() local
119 for (index = 0U; index < NUM_STATIC_REGIONS; index++) in rt_hw_mpu_init()
125 static_regions[index].attr.rasr = _mpu_rasr(&(static_regions[index])); in rt_hw_mpu_init()
126 …ARM_MPU_SetRegion(ARM_MPU_RBAR(index, (rt_uint32_t)static_regions[index].start), static_regions[in… in rt_hw_mpu_init()
136 rt_uint8_t index; in rt_hw_mpu_add_region() local
167 rt_uint8_t index; in rt_hw_mpu_delete_region() local
180 ARM_MPU_ClrRegion(index); in rt_hw_mpu_delete_region()
188 rt_uint8_t index; in rt_hw_mpu_update_region() local
230 index += 1U; in rt_hw_mpu_table_switch()
239 index += 1U; in rt_hw_mpu_table_switch()
[all …]
/libcpu/arm/AT91SAM7S/
A Dinterrupt.c36 rt_base_t index; in rt_hw_interrupt_init() local
38 for (index = 0; index < MAX_HANDLERS; index ++) in rt_hw_interrupt_init()
40 AT91C_AIC_SVR(index) = (rt_uint32_t)rt_hw_interrupt_handler; in rt_hw_interrupt_init()
/libcpu/arm/lpc214x/
A Dcpuport.c85 rt_base_t index; in rt_hw_interrupt_init() local
95 for (index = 0; index < MAX_HANDLERS; index ++) in rt_hw_interrupt_init()
97 irq_desc[index].handler = rt_hw_interrupt_handler; in rt_hw_interrupt_init()
99 vect_addr = (rt_uint32_t *)(VIC_BASE_ADDR + 0x100 + (index << 2)); in rt_hw_interrupt_init()
100 vect_ctl = (rt_uint32_t *)(VIC_BASE_ADDR + 0x200 + (index << 2)); in rt_hw_interrupt_init()
102 *vect_addr = (rt_uint32_t)&irq_desc[index]; in rt_hw_interrupt_init()
/libcpu/mips/gs264/
A Dmips_mmu.c68 void mmu_tlb_write_indexed(uint32_t index,tlb_item_t *tlb_item) in mmu_tlb_write_indexed() argument
72 mmu_tlb_set_index(index); in mmu_tlb_write_indexed()
93 void mmu_tlb_read(uint32_t index,tlb_item_t *tlb_item) in mmu_tlb_read() argument
95 mmu_tlb_set_index(index); in mmu_tlb_read()
129 *index = mmu_tlb_get_index(); in mmu_tlb_find()
155 uint32_t index; in mmu_set_map() local
162 if(mmu_tlb_find(vpn & (~lb),asid,&index)) in mmu_set_map()
164 mmu_tlb_read(index,&tlb_item); in mmu_set_map()
165 mmu_tlb_write_indexed(index,&tlb2_item); in mmu_set_map()
191 void mmu_tlb_set_index(uint32_t index) in mmu_tlb_set_index() argument
[all …]
A Dmips_mmu.h85 void mmu_tlb_write_indexed(uint32_t index,tlb_item_t *tlb_item);
87 void mmu_tlb_read(uint32_t index,tlb_item_t *tlb_item);
88 uint32_t mmu_tlb_find(uint64_t vpn,uint32_t asid,uint32_t *index);
93 void mmu_tlb_set_index(uint32_t index);
/libcpu/xilinx/microblaze/
A Dtrap.c44 rt_base_t index; in rt_hw_interrupt_init() local
52 for (index = 0; index < MAX_HANDLERS; index ++) in rt_hw_interrupt_init()
54 CfgPtr->HandlerTable[index].Handler = (XInterruptHandler)rt_hw_interrupt_handler; in rt_hw_interrupt_init()
/libcpu/risc-v/common64/
A Dcontext_gcc.S20 .macro SAVE_REG reg, index
21 STORE \reg, \index*REGBYTES(sp)
24 .macro LOAD_REG reg, index
25 LOAD \reg, \index*REGBYTES(sp)
/libcpu/arm/am335x/
A Dmmu.c102 void mmu_clean_invalidated_cache_index(int index) in mmu_clean_invalidated_cache_index() argument
104 asm volatile ("mcr p15, 0, %0, c7, c14, 2": :"r" (index)); in mmu_clean_invalidated_cache_index()

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