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Searched refs:isb (Results 1 – 15 of 15) sorted by relevance

/libcpu/arm/cortex-r52/
A Dcp15_gcc.S52 isb
70 isb @ isb to sych the new cssr&csidr
97 isb
114 isb
140 isb
149 isb
/libcpu/arm/zynqmp-r5/
A Dxil_mpu.c172 isb(); in Xil_SetMPURegion()
191 isb(); in Xil_SetMPURegion()
236 isb(); in Xil_EnableMPU()
290 isb(); in Xil_DisableMPU()
452 isb(); in Xil_DisableMPURegionByRegNum()
495 isb(); in Xil_SetMPURegionByRegNum()
514 isb(); in Xil_SetMPURegionByRegNum()
A Dmpu.c247 isb(); in Xil_SetAttribute()
252 isb(); /* synchronize context on this processor */ in Xil_SetAttribute()
281 isb(); in Xil_DisableMPURegions()
A Dxpseudo_asm_gcc.h98 #define isb() __asm__ __volatile__ ("isb sy") macro
163 #define isb() __asm__ __volatile__ ("isb" : : : "memory")
A Dstart_gcc.S89 isb
126isb /* Ensure subsequent insts execute wrt new MPU settings */
147 isb
192 isb /* isb flush prefetch buffer */
A Dcache.c300 isb(); in Xil_DCacheStoreLine()
/libcpu/arm/cortex-a/
A Dtlb.h19 #define isb() __asm__ volatile("isb" : : : "memory") macro
A Dcp15_gcc.S62 isb
88 isb
97 isb
A Dstart_gcc.S170 isb
177 isb
268 isb
649 isb
/libcpu/aarch64/common/
A Dcache.S24 isb /* sync change of cssidr_el1 */
95 isb
198 isb sy
A Dcpu_gcc.S150 isb
164 isb
/libcpu/aarch64/cortex-a/
A Dentry_point.S247 isb
323 isb
327 isb
331 isb
/libcpu/aarch64/common/include/
A Dcpuport.h36 #define rt_hw_isb() rt_hw_barrier(isb)
/libcpu/arm/realview-a8-vmm/
A Dcp15_gcc.S57 isb
83 isb
/libcpu/arm/am335x/
A Dcp15_gcc.S62 isb
88 isb

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