| /libcpu/risc-v/common64/ |
| A D | tlb.h | 27 uintptr_t mask = -1ul; in rt_hw_tlb_invalidate_all() local
28 HANDLE_FAULT(sbi_remote_sfence_vma(&mask, -1ul, 0, mask)); in rt_hw_tlb_invalidate_all()
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| /libcpu/arm/cortex-r52/ |
| A D | backtrace.c | 224 unsigned long mask) in unwind_exec_pop_subset_r4_to_r13() argument
230 while (mask) in unwind_exec_pop_subset_r4_to_r13()
232 if (mask & 1) in unwind_exec_pop_subset_r4_to_r13()
235 mask >>= 1; in unwind_exec_pop_subset_r4_to_r13()
265 unsigned long mask) in unwind_exec_pop_subset_r0_to_r3() argument
271 while (mask) in unwind_exec_pop_subset_r0_to_r3()
273 if (mask & 1) in unwind_exec_pop_subset_r0_to_r3()
276 mask >>= 1; in unwind_exec_pop_subset_r0_to_r3()
300 unsigned long mask; in unwind_exec_insn() local
304 if (mask == 0) in unwind_exec_insn()
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| A D | gicv3.c | 78 rt_uint32_t mask = 1U << (irq % 32U); in arm_gic_mask() local
99 rt_uint32_t mask = 1U << (irq % 32U); in arm_gic_umask() local
170 rt_uint32_t mask; in arm_gic_clear_pending_irq() local
179 mask = 1U << (irq % 32U); in arm_gic_clear_pending_irq()
184 mask = 1U << ((irq % 4U) * 8U); in arm_gic_clear_pending_irq()
220 rt_uint32_t mask = 1U << (irq % 32U); in arm_gic_clear_active() local
260 rt_uint32_t mask; in arm_gic_set_priority() local
273 mask &= ~(0xFFUL << ((irq % 4U) * 8U)); in arm_gic_set_priority()
274 mask |= ((priority & 0xFFUL) << ((irq % 4U) * 8U)); in arm_gic_set_priority()
280 mask &= ~(0xFFUL << ((irq % 4U) * 8U)); in arm_gic_set_priority()
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| A D | cp15_gcc.S | 66 and r1, r1, #7 @ mask of the bits for current cache only
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| /libcpu/arm/cortex-a/ |
| A D | backtrace.c | 223 unsigned long mask) in unwind_exec_pop_subset_r4_to_r13() argument
229 while (mask) in unwind_exec_pop_subset_r4_to_r13()
231 if (mask & 1) in unwind_exec_pop_subset_r4_to_r13()
234 mask >>= 1; in unwind_exec_pop_subset_r4_to_r13()
264 unsigned long mask) in unwind_exec_pop_subset_r0_to_r3() argument
270 while (mask) in unwind_exec_pop_subset_r0_to_r3()
272 if (mask & 1) in unwind_exec_pop_subset_r0_to_r3()
275 mask >>= 1; in unwind_exec_pop_subset_r0_to_r3()
299 unsigned long mask; in unwind_exec_insn() local
303 if (mask == 0) in unwind_exec_insn()
[all …]
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| A D | gicv3.c | 79 rt_uint32_t mask = 1U << (irq % 32U); in arm_gic_mask() local
100 rt_uint32_t mask = 1U << (irq % 32U); in arm_gic_umask() local
171 rt_uint32_t mask; in arm_gic_clear_pending_irq() local
180 mask = 1U << (irq % 32U); in arm_gic_clear_pending_irq()
185 mask = 1U << ((irq % 4U) * 8U); in arm_gic_clear_pending_irq()
221 rt_uint32_t mask = 1U << (irq % 32U); in arm_gic_clear_active() local
261 rt_uint32_t mask; in arm_gic_set_priority() local
274 mask &= ~(0xFFUL << ((irq % 4U) * 8U)); in arm_gic_set_priority()
275 mask |= ((priority & 0xFFUL) << ((irq % 4U) * 8U)); in arm_gic_set_priority()
281 mask &= ~(0xFFUL << ((irq % 4U) * 8U)); in arm_gic_set_priority()
[all …]
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| A D | gic.c | 76 rt_uint32_t mask = 1U << (irq % 32U); in arm_gic_ack() local
89 rt_uint32_t mask = 1U << (irq % 32U); in arm_gic_mask() local
101 rt_uint32_t mask = 1U << (irq % 32U); in arm_gic_umask() local
163 rt_uint32_t mask; in arm_gic_clear_pending_irq() local
172 mask = 1U << (irq % 32U); in arm_gic_clear_pending_irq()
177 mask = 1U << ((irq % 4U) * 8U); in arm_gic_clear_pending_irq()
213 rt_uint32_t mask = 1U << (irq % 32U); in arm_gic_clear_active() local
253 rt_uint32_t mask; in arm_gic_set_priority() local
260 mask = GIC_DIST_PRI(_gic_table[index].dist_hw_base, irq); in arm_gic_set_priority()
261 mask &= ~(0xFFUL << ((irq % 4U) * 8U)); in arm_gic_set_priority()
[all …]
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| /libcpu/aarch64/common/ |
| A D | gic.c | 78 rt_uint64_t mask = 1U << (irq % 32U); in arm_gic_ack() local
91 rt_uint64_t mask = 1U << (irq % 32U); in arm_gic_mask() local
103 rt_uint64_t mask = 1U << (irq % 32U); in arm_gic_umask() local
165 rt_uint64_t mask; in arm_gic_clear_pending_irq() local
174 mask = 1U << (irq % 32U); in arm_gic_clear_pending_irq()
179 mask = 1U << ((irq % 4U) * 8U); in arm_gic_clear_pending_irq()
215 rt_uint64_t mask = 1U << (irq % 32U); in arm_gic_clear_active() local
255 rt_uint64_t mask; in arm_gic_set_priority() local
262 mask = GIC_DIST_PRI(_gic_table[index].dist_hw_base, irq); in arm_gic_set_priority()
263 mask &= ~(0xFFUL << ((irq % 4U) * 8U)); in arm_gic_set_priority()
[all …]
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| A D | gicv3.c | 71 rt_uint64_t mask = 1 << (irq % 32); in arm_gic_mask() local
92 rt_uint64_t mask = 1 << (irq % 32); in arm_gic_umask() local
163 rt_uint64_t mask; in arm_gic_clear_pending_irq() local
172 mask = 1 << (irq % 32); in arm_gic_clear_pending_irq()
177 mask = 1 << ((irq % 4) * 8); in arm_gic_clear_pending_irq()
213 rt_uint64_t mask = 1 << (irq % 32); in arm_gic_clear_active() local
273 rt_uint64_t mask; in arm_gic_set_priority() local
285 mask &= ~(0xffUL << ((irq % 4) * 8)); in arm_gic_set_priority()
286 mask |= ((priority & 0xff) << ((irq % 4) * 8)); in arm_gic_set_priority()
292 mask &= ~(0xff << ((irq % 4) * 8)); in arm_gic_set_priority()
[all …]
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| /libcpu/arm/realview-a8-vmm/ |
| A D | gic.c | 66 rt_uint32_t mask = 1 << (irq % 32); in arm_gic_ack() local
73 GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; in arm_gic_ack()
75 GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask; in arm_gic_ack()
80 rt_uint32_t mask = 1 << (irq % 32); in arm_gic_mask() local
87 GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; in arm_gic_mask()
92 rt_uint32_t mask = 1 << (irq % 32); in arm_gic_clear_pending() local
99 GIC_DIST_PENDING_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; in arm_gic_clear_pending()
104 rt_uint32_t mask = 1 << (irq % 32); in arm_gic_clear_active() local
111 GIC_DIST_ACTIVE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; in arm_gic_clear_active()
133 rt_uint32_t mask = 1 << (irq % 32); in arm_gic_umask() local
[all …]
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| /libcpu/arm/zynqmp-r5/ |
| A D | gic.c | 65 rt_uint32_t mask = 1 << (irq % 32); in arm_gic_ack() local
72 GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; in arm_gic_ack()
74 GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask; in arm_gic_ack()
79 rt_uint32_t mask = 1 << (irq % 32); in arm_gic_mask() local
86 GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; in arm_gic_mask()
108 rt_uint32_t mask = 1 << (irq % 32); in arm_gic_umask() local
115 GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask; in arm_gic_umask()
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| /libcpu/ti-dsp/c6x/ |
| A D | trap.h | 23 #define set_iexcept(mask) IERR = (mask) argument
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| /libcpu/arm/armv6/ |
| A D | arm_entry_gcc.S | 70 .word 0xfe000000 @ mask
73 .word 0xff100000 @ mask
76 .word 0x00000000 @ end mask
91 ldr r7, [r6], #4 @ load mask value
92 cmp r7, #0 @ end mask?
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| /libcpu/mips/gs264/ |
| A D | mips_mmu.h | 38 uint64_t mask : 18; member
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| A D | mips_mmu.c | 160 tlb_item.page_mask.mask = page_mask; in mmu_set_map()
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| /libcpu/arm/am335x/ |
| A D | start_iar.s | 16 MODE_MSK DEFINE 0x1F ; Bit mask for mode bits in CPSR
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| /libcpu/ti-dsp/c28x/ |
| A D | context.s | 191 ; mask out non-critical interrupts and enable global interrupt
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