Searched refs:mcr (Results 1 – 22 of 22) sorted by relevance

/libcpu/arm/cortex-a/
A D	cp15_gcc.S	21 mcr p15, #0, r1, c1, c0, #0 23 mcr p15, #0, r0, c12, c0, #0 31 mcr p15, #0, r0, c1, c0, #0 38 mcr p15, #0, r0, c1, c0, #0 61 mcr p15, #2, r10, c0, c0, #0 76 mcr p15, #0, r11, c7, c14, #2 106 mcr p15, #0, r0, c1, c0, #0 114 mcr p15, #0, r0, c1, c0, #0 119 mcr p15, #0, r0, c8, c7, #0 @ invalidate tlb 122 mcr p15, #0, r0, c1, c0, #0 @ clear mmu bit [all …]
A D	start_gcc.S	71 mcr p15, 0, r4, c1, c0, 2 82 mcr p15, 0, r0, c1, c0, 0 168 mcr p15, 0, r0, c1, c0, 0 173 mcr p15, 0, r0, c8, c7, 0 175 mcr p15, 0, r0, c7, c5, 6 /* bpiall */ 219 mcr p15, #0, r0, c2, c0, #0 223 mcr p15, #0, r0, c3, c0, #0 227 mcr p15, 0, r0, c2, c0, 2 /* ttbcr */ 258 mcr p15, 0, r0, c8, c7, 0 266 mcr p15, 0, r0, c1, c0, 0 [all …]
/libcpu/arm/arm926/
A D	mmu.c	25 __asm volatile{ mcr p15, 0, value, c8, c7, 0 } in mmu_setttbase() 28 __asm volatile { mcr p15, 0, i, c2, c0, 0 } in mmu_setttbase() 33 __asm volatile { mcr p15, 0, i, c3, c0, 0 } in mmu_set_domain() 44 mcr p15, 0, value, c1, c0, 0 in mmu_enable() 56 mcr p15, 0, value, c1, c0, 0 in mmu_disable() 68 mcr p15, 0, value, c1, c0, 0 in mmu_enable_icache() 80 mcr p15, 0, value, c1, c0, 0 in mmu_enable_dcache() 92 mcr p15, 0, value, c1, c0, 0 in mmu_disable_icache() 104 mcr p15, 0, value, c1, c0, 0 in mmu_disable_dcache() 116 mcr p15, 0, value, c1, c0, 0 in mmu_enable_alignfault() [all …]
A D	cpuport.c	74 mcr p15, 0, value, c1, c0, 0 in cache_enable() 86 mcr p15, 0, value, c1, c0, 0 in cache_disable()
A D	start_gcc.S	169 mcr p15, 0, r0, c7, c7, 0 170 mcr p15, 0, r0, c8, c7, 0 178 mcr p15, 0, r0, c1, c0, 0
/libcpu/arm/s3c24x0/
A D	mmu.c	175 mcr p15, 0, i, c2, c0, 0 in mmu_setttbase() 183 mcr p15,0, i, c3, c0, 0 in mmu_set_domain() 195 mcr p15, 0, value, c1, c0, 0 in mmu_enable() 207 mcr p15, 0, value, c1, c0, 0 in mmu_disable() 219 mcr p15, 0, value, c1, c0, 0 in mmu_enable_icache() 231 mcr p15, 0, value, c1, c0, 0 in mmu_enable_dcache() 243 mcr p15, 0, value, c1, c0, 0 in mmu_disable_icache() 255 mcr p15, 0, value, c1, c0, 0 in mmu_disable_dcache() 267 mcr p15, 0, value, c1, c0, 0 in mmu_enable_alignfault() 279 mcr p15, 0, value, c1, c0, 0 in mmu_disable_alignfault() [all …]
A D	cpu.c	76 mcr p15, 0, value, c1, c0, 0 in cache_enable() 88 mcr p15, 0, value, c1, c0, 0 in cache_disable()
/libcpu/arm/realview-a8-vmm/
A D	cp15_gcc.S	18 mcr p15, #0, r0, c12, c0, #0 26 mcr p15, #0, r0, c1, c0, #0 33 mcr p15, #0, r0, c1, c0, #0 56 mcr p15, #2, r10, c0, c0, #0 71 mcr p15, #0, r11, c7, c14, #2 93 mcr p15, #0, r0, c1, c0, #0 101 mcr p15, #0, r0, c1, c0, #0 106 mcr p15, #0, r0, c8, c7, #0 @ invalidate tlb 109 mcr p15, #0, r0, c1, c0, #0 @ clear mmu bit 117 mcr p15, #0, r0, c1, c0, #0 @ set mmu enable bit [all …]
/libcpu/arm/am335x/
A D	cp15_gcc.S	13 mcr p15, #0, r0, c12, c0, #0 31 mcr p15, #0, r0, c1, c0, #0 38 mcr p15, #0, r0, c1, c0, #0 61 mcr p15, #2, r10, c0, c0, #0 76 mcr p15, #0, r11, c7, c14, #2 97 mcr p15, #0, r0, c1, c0, #0 106 mcr p15, #0, r0, c1, c0, #0 111 mcr p15, #0, r0, c8, c7, #0 @ invalidate tlb 114 mcr p15, #0, r0, c1, c0, #0 @ clear mmu bit 122 mcr p15, #0, r0, c1, c0, #0 @ set mmu enable bit [all …]
A D	cpu.c	46 mcr p15, 0, value, c1, c0, 0 in cache_enable() 58 mcr p15, 0, value, c1, c0, 0 in cache_disable()
/libcpu/arm/dm36x/
A D	mmu.c	25 mcr p15, 0, value, c8, c7, 0 in mmu_setttbase() 31 mcr p15, 0, value, c3, c0, 0 in mmu_setttbase() 32 mcr p15, 0, i, c2, c0, 0 in mmu_setttbase() 40 mcr p15,0, i, c3, c0, 0 in mmu_set_domain() 52 mcr p15, 0, value, c1, c0, 0 in mmu_enable() 64 mcr p15, 0, value, c1, c0, 0 in mmu_disable() 76 mcr p15, 0, value, c1, c0, 0 in mmu_enable_icache() 88 mcr p15, 0, value, c1, c0, 0 in mmu_enable_dcache() 100 mcr p15, 0, value, c1, c0, 0 in mmu_disable_icache() 112 mcr p15, 0, value, c1, c0, 0 in mmu_disable_dcache() [all …]
A D	cpuport.c	73 mcr p15, 0, value, c1, c0, 0 in cache_enable() 85 mcr p15, 0, value, c1, c0, 0 in cache_disable()
/libcpu/arm/armv6/
A D	mmu.c	25 mcr p15, 0, value, c8, c7, 0 in mmu_setttbase() 31 mcr p15, 0, value, c3, c0, 0 in mmu_setttbase() 32 mcr p15, 0, i, c2, c0, 0 in mmu_setttbase() 40 mcr p15,0, i, c3, c0, 0 in mmu_set_domain() 52 mcr p15, 0, value, c1, c0, 0 in mmu_enable() 64 mcr p15, 0, value, c1, c0, 0 in mmu_disable() 76 mcr p15, 0, value, c1, c0, 0 in mmu_enable_icache() 144 mcr p15, 0, index, c7, c14, 2 in mmu_clean_invalidated_cache_index() 203 mcr p15, 0, value, c8, c7, 0 in mmu_invalidate_tlb() 215 mcr p15, 0, value, c7, c5, 0 in mmu_invalidate_icache() [all …]
A D	cpuport.c	75 mcr p15, 0, value, c1, c0, 0 in cache_enable() 87 mcr p15, 0, value, c1, c0, 0 in cache_disable()
/libcpu/arm/cortex-r52/
A D	cp15_gcc.S	20 mcr p15, #0, r1, c1, c0, #0 22 mcr p15, #0, r0, c12, c0, #0 30 mcr p15, #0, r0, c1, c0, #0 37 mcr p15, #0, r0, c1, c0, #0 50 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate 84 mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way 113 mcr p15, #2, r10, c0, c0, #0 128 mcr p15, #0, r11, c7, c14, #2 147 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate 158 mcr p15, #0, r0, c1, c0, #0 [all …]
A D	start_iar.S	77 mcr p15, #0x00, r0, c1, c0, #0x01 90 mcr p15, #0x00, r0, c1, c0, #0x01 104 mcr p15, #0x00, r0, c1, c0, #0x01 117 mcr p15, #0x00, r0, c1, c0, #0x01 138 mcr p15, #0, r0, c5, c0, #0 159 mcr p15, #0, r0, c5, c0, #1 180 mcr p15, #0, r0, c6, c0, #0 201 mcr p15, #0, r0, c6, c0, #2 224 mcr p15, #0, r0, c5, c1, #0 267 mcr p15, #0, r0, c15, c0, #0 ;@ Write Secondary Auxiliary Control Register [all …]
A D	start_gcc.S	78 mcr p15, #0x00, r2, c1, c0, #0x02 177 mcr p15, #0x00, r0, c1, c0, #0x01 190 mcr p15, #0x00, r0, c1, c0, #0x01 205 mcr p15, #0x00, r0, c1, c0, #0x01 218 mcr p15, #0x00, r0, c1, c0, #0x01 242 mcr p15, #0, r0, c5, c0, #0 267 mcr p15, #0, r0, c5, c0, #1 292 mcr p15, #0, r0, c6, c0, #0 317 mcr p15, #0, r0, c6, c0, #2 342 mcr p15, #0, r0, c5, c1, #0 [all …]
/libcpu/arm/cortex-r4/
A D	start_ccs.asm	70 mcr p15, #0x00, r2, c1, c0, #0x02 142 mcr p15, #0x00, r0, c1, c0, #0x01 160 mcr p15, #0x00, r0, c1, c0, #0x01 179 mcr p15, #0x00, r0, c1, c0, #0x01 197 mcr p15, #0x00, r0, c1, c0, #0x01 227 mcr p15, #0, r0, c5, c0, #0 258 mcr p15, #0, r0, c5, c0, #1 289 mcr p15, #0, r0, c6, c0, #0 320 mcr p15, #0, r0, c6, c0, #2 351 mcr p15, #0, r0, c5, c1, #0 [all …]
A D	start_gcc.S	80 mcr p15, #0x00, r2, c1, c0, #0x02 179 mcr p15, #0x00, r0, c1, c0, #0x01 192 mcr p15, #0x00, r0, c1, c0, #0x01 207 mcr p15, #0x00, r0, c1, c0, #0x01 220 mcr p15, #0x00, r0, c1, c0, #0x01 244 mcr p15, #0, r0, c5, c0, #0 269 mcr p15, #0, r0, c5, c0, #1 294 mcr p15, #0, r0, c6, c0, #0 319 mcr p15, #0, r0, c6, c0, #2 344 mcr p15, #0, r0, c5, c1, #0 [all …]
/libcpu/arm/zynqmp-r5/
A D	start_gcc.S	88 mcr p15, 0, r0, c1, c0, 2 /* Write Coprocessor Access Control Register (CPACR) */ 125 mcr p15, 0, r0, c1, c0, 0 /* Write CP15 Control Register */ 139 mcr p15, 0, r0, c1, c0, 1 /* Write ACTLR*/ 145 mcr p15, 0, r0, c7, c5, 0 /* invalidate icache */ 146 mcr p15, 0, r0, c15, c5, 0 /* Invalidate entire data cache*/ 184 mcr p15, 0, r0, c1, c0, 1 /* Write ACTLR*/ 191 mcr p15,0,r1,c1,c0,0 /* Enable cache */ 198 mcr p15, 0, r0, c1, c0, 0
/libcpu/arm/sep4020/
A D	serial.h	65 rt_uint32_t mcr; member
/libcpu/unicore32/sep6200/
A D	serial.h	72 rt_uint32_t mcr; member

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Last Index update Fri Aug 22 02:45:11 CST 2025