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Searched refs:mdesc (Results 1 – 13 of 13) sorted by relevance

/libcpu/arm/dm36x/
A Dmmu.c436 nSec = (mdesc->vaddr_end >> 20) - (mdesc->vaddr_start >> 20); in mmu_create_pgd()
439 *pTT = mdesc->sect_attr | (((mdesc->paddr_start >> 20) + i) << 20); in mmu_create_pgd()
454 total_page = (mdesc->vaddr_end >> 12) - (mdesc->vaddr_start >> 12) + 1; in mmu_create_pte()
457 vaddr = mdesc->vaddr_start; in mmu_create_pte()
476 *p_pteentry = mdesc->page_attr | (((mdesc->paddr_start >> 12) + i) << 12); in mmu_create_pte()
490 … nsec = (RT_ALIGN(mdesc->vaddr_end, 0x100000) - RT_ALIGN_DOWN(mdesc->vaddr_start, 0x100000)) >> 20; in build_pte_mem_desc()
500 mdesc++; in build_pte_mem_desc()
515 build_pte_mem_desc(mdesc, size); in rt_hw_mmu_init()
521 mmu_create_pgd(mdesc); in rt_hw_mmu_init()
525 mmu_create_pte(mdesc); in rt_hw_mmu_init()
[all …]
A Dmmu.h147 void rt_hw_mmu_init(struct mem_desc *mdesc, rt_uint32_t size);
/libcpu/arm/armv6/
A Dmmu.c437 nSec = (mdesc->vaddr_end >> 20) - (mdesc->vaddr_start >> 20); in mmu_create_pgd()
440 *pTT = mdesc->sect_attr | (((mdesc->paddr_start >> 20) + i) << 20); in mmu_create_pgd()
455 total_page = (mdesc->vaddr_end >> 12) - (mdesc->vaddr_start >> 12) + 1; in mmu_create_pte()
458 vaddr = mdesc->vaddr_start; in mmu_create_pte()
477 *p_pteentry = mdesc->page_attr | (((mdesc->paddr_start >> 12) + i) << 12); in mmu_create_pte()
491 … nsec = (RT_ALIGN(mdesc->vaddr_end, 0x100000) - RT_ALIGN_DOWN(mdesc->vaddr_start, 0x100000)) >> 20; in build_pte_mem_desc()
501 mdesc++; in build_pte_mem_desc()
517 build_pte_mem_desc(mdesc, size); in rt_hw_mmu_init()
523 mmu_create_pgd(mdesc); in rt_hw_mmu_init()
527 mmu_create_pte(mdesc); in rt_hw_mmu_init()
[all …]
A Dmmu.h191 void rt_hw_mmu_init(struct mem_desc *mdesc, rt_uint32_t size);
/libcpu/arm/cortex-a/
A Dmmu.c122 void rt_hw_init_mmu_table(struct mem_desc *mdesc, rt_uint32_t size) in rt_hw_init_mmu_table() argument
136 if (mdesc->paddr_start == (rt_uint32_t)ARCH_MAP_FAILED) in rt_hw_init_mmu_table()
137 mdesc->paddr_start = mdesc->vaddr_start + PV_OFFSET; in rt_hw_init_mmu_table()
139 vaddr = (void *)mdesc->vaddr_start; in rt_hw_init_mmu_table()
140 length = mdesc->vaddr_end - mdesc->vaddr_start; in rt_hw_init_mmu_table()
141 rt_aspace_map_static(&rt_kernel_space, &mdesc->varea, &vaddr, length, in rt_hw_init_mmu_table()
142 mdesc->attr, MMF_MAP_FIXED, &rt_mm_dummy_mapper, 0); in rt_hw_init_mmu_table()
144 rt_hw_mmu_setmtt(mdesc->vaddr_start, mdesc->vaddr_end, in rt_hw_init_mmu_table()
145 mdesc->paddr_start, mdesc->attr); in rt_hw_init_mmu_table()
146 mdesc++; in rt_hw_init_mmu_table()
A Dmmu.h112 void rt_hw_init_mmu_table(struct mem_desc *mdesc, rt_uint32_t size);
114 void rt_hw_mmu_setup(struct rt_aspace *aspace, struct mem_desc *mdesc, int desc_nr);
/libcpu/risc-v/common64/
A Dmmu.c607 void rt_hw_mmu_setup(rt_aspace_t aspace, struct mem_desc *mdesc, int desc_nr) in rt_hw_mmu_setup() argument
613 switch (mdesc->attr) in rt_hw_mmu_setup()
632 .map_size = mdesc->vaddr_end - mdesc->vaddr_start + 1, in rt_hw_mmu_setup()
633 .prefer = (void *)mdesc->vaddr_start}; in rt_hw_mmu_setup()
635 if (mdesc->paddr_start == (rt_uintptr_t)ARCH_MAP_FAILED) in rt_hw_mmu_setup()
636 mdesc->paddr_start = mdesc->vaddr_start + PV_OFFSET; in rt_hw_mmu_setup()
638 rt_aspace_map_phy_static(aspace, &mdesc->varea, &hint, attr, in rt_hw_mmu_setup()
639 mdesc->paddr_start >> MM_PAGE_SHIFT, &err); in rt_hw_mmu_setup()
640 mdesc++; in rt_hw_mmu_setup()
A Dmmu.h62 void rt_hw_mmu_setup(rt_aspace_t aspace, struct mem_desc *mdesc, int desc_nr);
/libcpu/arm/arm926/
A Dmmu.c413 void rt_hw_mmu_init(struct mem_desc *mdesc, rt_uint32_t size) in rt_hw_mmu_init() argument
424 mmu_setmtt(mdesc->vaddr_start, mdesc->vaddr_end, in rt_hw_mmu_init()
425 mdesc->paddr_start, mdesc->attr); in rt_hw_mmu_init()
426 mdesc++; in rt_hw_mmu_init()
A Dmmu.h48 void rt_hw_mmu_init(struct mem_desc *mdesc, rt_uint32_t size);
/libcpu/aarch64/common/
A Dmmu.c467 void rt_hw_mmu_setup(rt_aspace_t aspace, struct mem_desc *mdesc, int desc_nr) in rt_hw_mmu_setup() argument
473 switch (mdesc->attr) in rt_hw_mmu_setup()
491 .map_size = mdesc->vaddr_end - in rt_hw_mmu_setup()
492 mdesc->vaddr_start + 1, in rt_hw_mmu_setup()
493 .prefer = (void *)mdesc->vaddr_start}; in rt_hw_mmu_setup()
495 if (mdesc->paddr_start == (rt_size_t)ARCH_MAP_FAILED) in rt_hw_mmu_setup()
496 mdesc->paddr_start = mdesc->vaddr_start + PV_OFFSET; in rt_hw_mmu_setup()
498 retval = rt_aspace_map_phy_static(aspace, &mdesc->varea, &hint, attr, in rt_hw_mmu_setup()
499 mdesc->paddr_start >> MM_PAGE_SHIFT, &err); in rt_hw_mmu_setup()
505 mdesc++; in rt_hw_mmu_setup()
/libcpu/mips/gs264/
A Dmmu.c172 void rt_hw_init_mmu_table(struct mem_desc *mdesc, rt_uint32_t size) in rt_hw_init_mmu_table() argument
177 rt_hw_mmu_setmtt(mdesc->vaddr_start, mdesc->vaddr_end, in rt_hw_init_mmu_table()
178 mdesc->paddr_start, mdesc->attr); in rt_hw_init_mmu_table()
179 mdesc++; in rt_hw_init_mmu_table()
/libcpu/aarch64/common/include/
A Dmmu.h109 void rt_hw_mmu_setup(struct rt_aspace *aspace, struct mem_desc *mdesc,

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