Searched refs:mfcp (Results 1 – 4 of 4) sorted by relevance
| /libcpu/arm/zynqmp-r5/ |
| A D | cache.c | 72 CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); in Xil_DCacheEnable()
74 mfcp(XREG_CP15_SYS_CONTROL, CtrlReg); in Xil_DCacheEnable()
97 CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); in Xil_DCacheDisable()
99 mfcp(XREG_CP15_SYS_CONTROL, CtrlReg); in Xil_DCacheDisable()
199 mfcp(XREG_CP15_CACHE_SIZE_ID, CsidReg); in Xil_DCacheFlush()
311 CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); in Xil_ICacheEnable()
313 mfcp(XREG_CP15_SYS_CONTROL, CtrlReg); in Xil_ICacheEnable()
338 CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); in Xil_ICacheDisable()
340 mfcp(XREG_CP15_SYS_CONTROL, CtrlReg); in Xil_ICacheDisable()
435 mfcp(XREG_CP15_SYS_CONTROL, CtrlReg); in rt_hw_cpu_icache_status()
[all …]
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| A D | xil_mpu.c | 211 CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); in Xil_EnableMPU()
213 mfcp(XREG_CP15_SYS_CONTROL,CtrlReg); in Xil_EnableMPU()
229 Reg = mfcp(XREG_CP15_SYS_CONTROL); in Xil_EnableMPU()
231 mfcp(XREG_CP15_SYS_CONTROL,Reg); in Xil_EnableMPU()
263 CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); in Xil_DisableMPU()
265 mfcp(XREG_CP15_SYS_CONTROL,CtrlReg); in Xil_DisableMPU()
283 Reg = mfcp(XREG_CP15_SYS_CONTROL); in Xil_DisableMPU()
285 mfcp(XREG_CP15_SYS_CONTROL,Reg); in Xil_DisableMPU()
444 Temp = mfcp(XREG_CP15_MPU_REG_SIZE_EN); in Xil_DisableMPURegionByRegNum()
446 mfcp(XREG_CP15_MPU_REG_SIZE_EN,Temp); in Xil_DisableMPURegionByRegNum()
[all …]
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| A D | xpseudo_asm_gcc.h | 218 #define mfcp(reg) ({u64 rval = 0U;\ macro
232 #define mfcp(rn) ({rt_uint32_t rval = 0U; \
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| A D | mpu.c | 273 Temp = mfcp(XREG_CP15_MPU_REG_SIZE_EN); in Xil_DisableMPURegions()
275 mfcp(XREG_CP15_MPU_REG_SIZE_EN,Temp); in Xil_DisableMPURegions()
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