Searched refs:msr (Results 1 – 25 of 42) sorted by relevance

12

/libcpu/aarch64/cortex-a/
A D	entry_point.S	103 msr tpidr_el1, xzr 190 msr scr_el3, x1 197 msr spsr_el3, x1 200 msr elr_el3, x1 218 msr hcr_el2, x0 225 msr spsr_el2, x0 228 msr elr_el2, x0 235 msr sctlr_el1, x0 243 msr cpacr_el1, x0 276 msr spsel, #1 [all …]
/libcpu/ppc/common/
A D	stack.c	32 rt_uint32_t msr; in rt_hw_stack_init() local 34 __asm__ __volatile__("mfmsr %0\n" : "=r" (msr)); in rt_hw_stack_init() 35 msr |= 0x00028000; in rt_hw_stack_init() 39 *(--stk) = msr; /* srr0: machine status register */ in rt_hw_stack_init()
A D	ptrace.h	26 PPC_REG msr; member 47 #define user_mode(regs) (((regs)->msr & MSR_PR) != 0)
/libcpu/arm/AT91SAM7S/
A D	context_gcc.S	20 msr cpsr_c, r1 28 msr cpsr, r0 50 msr spsr_cxsf, r4 52 msr cpsr_cxsf, r4 65 msr spsr_cxsf, r4 67 msr cpsr_cxsf, r4
A D	start_gcc.S	104 msr cpsr_c, #MODE_UND|I_BIT|F_BIT 109 msr cpsr_c, #MODE_ABT|I_BIT|F_BIT 114 msr cpsr_c, #MODE_FIQ|I_BIT|F_BIT 119 msr cpsr_c, #MODE_IRQ|I_BIT|F_BIT 124 msr cpsr_c, #MODE_SVC 205 msr spsr_c, r0 229 msr SPSR_cxsf, r4 231 msr CPSR_cxsf, r4
/libcpu/aarch64/common/mp/
A D	context_gcc.h	30 msr spsr_el1, x3 31 msr elr_el1, x2 34 msr sp_el0, x29 36 msr fpcr, x28 37 msr fpsr, x29
/libcpu/ppc/ppc405/
A D	traps.c	65 regs->msr, regs->msr&MSR_EE ? 1 : 0, regs->msr&MSR_PR ? 1 : 0, in show_regs() 66 regs->msr & MSR_FP ? 1 : 0,regs->msr&MSR_ME ? 1 : 0, in show_regs() 67 regs->msr&MSR_IR ? 1 : 0, in show_regs() 68 regs->msr&MSR_DR ? 1 : 0); in show_regs() 200 regs->nip, regs->msr, regs->trap); in UnknownException()
/libcpu/aarch64/common/include/
A D	context_gcc.h	50 msr elr_el1, x30 51 msr spsr_el1, x19 56 msr fpcr, x19 57 msr fpsr, x20 60 msr sp_el0, x19
A D	vector_gcc.h	59 msr elr_el1, x2 60 msr spsr_el1, x3 65 msr fpcr, x28 66 msr fpsr, x29
/libcpu/aarch64/common/
A D	cpu_gcc.S	54 msr tpidrro_el0, x0 56 msr tpidr_el1, x0 96 msr CNTP_CTL_EL0, x0 148 msr DAIFSet, #3 170 msr DAIF, x0 209 msr VBAR_EL3,x0 212 msr VBAR_EL2,x0 215 msr VBAR_EL1,x0 233 msr SCR_EL3, x0 238 msr HCR_EL2, x0 [all …]
/libcpu/arm/s3c44b0/
A D	context_gcc.S	25 msr cpsr_c, r1 33 msr cpsr, r0 55 msr spsr_cxsf, r4 57 msr cpsr_cxsf, r4 70 msr spsr_cxsf, r4 72 msr cpsr_cxsf, r4
A D	start_gcc.S	74 msr cpsr_c, #SVCMODE|NOINT 199 msr SPSR_cxsf, r4 214 msr cpsr_c, #UNDEFMODE|NOINT 218 msr cpsr_c, #ABORTMODE|NOINT 222 msr cpsr_c, #FIQMODE|NOINT 226 msr cpsr_c, #IRQMODE|NOINT 230 msr cpsr_c, #SVCMODE|NOINT
/libcpu/arm/lpc24xx/
A D	context_gcc.S	25 msr cpsr_c, r1 33 msr cpsr, r0 55 msr spsr_cxsf, r4 57 msr cpsr_cxsf, r4 70 msr spsr_cxsf, r4 72 msr cpsr_cxsf, r4
A D	start_gcc.S	102 msr cpsr_c, #SVCMODE|NOINT 227 msr spsr_c, r0 251 msr SPSR_cxsf, r4 253 msr CPSR_cxsf, r4 261 msr cpsr_cxsf, r1 /* undef mode */ 265 msr cpsr_cxsf,r1 /* abort mode */ 269 msr cpsr_cxsf,r1 /* IRQ mode */ 273 msr cpsr_cxsf,r1 /* FIQ mode */ 278 msr cpsr_cxsf,r1 /* SVC mode */
/libcpu/arm/s3c24x0/
A D	context_gcc.S	25 msr cpsr_c, r1 33 msr cpsr, r0 55 msr spsr_cxsf, r4 57 msr spsr_cxsf, r4 70 msr spsr_cxsf, r4 72 msr cpsr_cxsf, r4
A D	start_gcc.S	171 msr cpsr,r0 327 msr spsr_c, r0 351 msr SPSR_cxsf, r4 353 msr CPSR_cxsf, r4 361 msr cpsr_cxsf, r1 /* undef mode */ 365 msr cpsr_cxsf,r1 /* abort mode */ 369 msr cpsr_cxsf,r1 /* IRQ mode */ 373 msr cpsr_cxsf,r1 /* FIQ mode */ 378 msr cpsr_cxsf,r1 /* SVC mode */
/libcpu/arm/AT91SAM7X/
A D	context_gcc.S	25 msr cpsr_c, r1 33 msr cpsr, r0 55 msr spsr_cxsf, r4 57 msr cpsr_cxsf, r4 70 msr spsr_cxsf, r4 72 msr cpsr_cxsf, r4
A D	start_gcc.S	116 msr cpsr_c, #MODE_UND|I_BIT|F_BIT 121 msr cpsr_c, #MODE_ABT|I_BIT|F_BIT 126 msr cpsr_c, #MODE_FIQ|I_BIT|F_BIT 131 msr cpsr_c, #MODE_IRQ|I_BIT|F_BIT 136 msr cpsr_c, #MODE_SVC|I_BIT|F_BIT 271 msr SPSR_cxsf, r4
/libcpu/arm/arm926/
A D	start_gcc.S	120 msr cpsr_cxsf, r0 188 msr cpsr_cxsf, r1 192 msr cpsr_cxsf, r1 196 msr cpsr_cxsf, r1 200 msr cpsr_cxsf, r1 204 msr cpsr_cxsf,r1 208 msr cpsr_cxsf, r1 250 msr cpsr_c, #I_BIT|F_BIT|MODE_SVC 267 msr spsr_cxsf, r4
/libcpu/arm/am335x/
A D	start_gcc.S	50 msr cpsr_c, r0 89 msr cpsr_c, #Mode_UND|I_Bit|F_Bit 94 msr cpsr_c, #Mode_ABT|I_Bit|F_Bit 99 msr cpsr_c, #Mode_FIQ|I_Bit|F_Bit 104 msr cpsr_c, #Mode_IRQ|I_Bit|F_Bit 109 msr cpsr_c, #Mode_SVC|I_Bit|F_Bit 129 msr cpsr_c, r2 132 msr cpsr_c, r1 @/* return to Undefined Instruction mode */ 233 msr cpsr_c, #I_Bit|F_Bit|Mode_SVC
/libcpu/arm/realview-a8-vmm/
A D	start_gcc.S	54 msr cpsr_c, r0 96 msr cpsr_c, #Mode_UND|I_Bit|F_Bit 101 msr cpsr_c, #Mode_ABT|I_Bit|F_Bit 106 msr cpsr_c, #Mode_FIQ|I_Bit|F_Bit 111 msr cpsr_c, #Mode_IRQ|I_Bit|F_Bit 116 msr cpsr_c, #Mode_SVC|I_Bit|F_Bit 188 msr spsr_cxsf, r4
A D	context_gcc.S	28 msr cpsr, r0 40 msr spsr_cxsf, r4
/libcpu/arm/dm36x/
A D	context_gcc.S	26 msr cpsr_c, r1 34 msr cpsr, r0
/libcpu/arm/lpc214x/
A D	startup_gcc.S	118 msr CPSR_c, #MODE_UND|I_BIT|F_BIT /* Undefined Instruction Mode */ 123 msr CPSR_c, #MODE_ABT|I_BIT|F_BIT /* Abort Mode */ 128 msr CPSR_c, #MODE_FIQ|I_BIT|F_BIT /* FIQ Mode */ 133 msr CPSR_c, #MODE_IRQ|I_BIT|F_BIT /* IRQ Mode */ 138 msr CPSR_c, #MODE_SVC|I_BIT|F_BIT /* Supervisor Mode */ 266 msr spsr_c, r0 /* 关闭SPSR中的IRQ/FIQ中断 */ 307 msr SPSR_cxsf, r4 310 msr CPSR_cxsf, r4
/libcpu/ppc/ppc405/include/asm/
A D	ptrace.h	31 PPC_REG msr; member 52 #define user_mode(regs) (((regs)->msr & MSR_PR) != 0)

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