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/libcpu/arm/realview-a8-vmm/
A Dinterrupt.h29 #define INTC_SCR(hw_base, n) REG32((hw_base) + 0x70 + ((n) * 0x04)) argument
30 #define INTC_ITR(hw_base, n) REG32((hw_base) + 0x80 + ((n) * 0x20)) argument
31 #define INTC_MIR(hw_base, n) REG32((hw_base) + 0x84 + ((n) * 0x20)) argument
32 #define INTC_MIR_CLEAR(hw_base, n) REG32((hw_base) + 0x88 + ((n) * 0x20)) argument
33 #define INTC_MIR_SET(hw_base, n) REG32((hw_base) + 0x8c + ((n) * 0x20)) argument
34 #define INTC_ISR_SET(hw_base, n) REG32((hw_base) + 0x90 + ((n) * 0x20)) argument
35 #define INTC_ISR_CLEAR(hw_base, n) REG32((hw_base) + 0x94 + ((n) * 0x20)) argument
36 #define INTC_PENDING_IRQ(hw_base, n) REG32((hw_base) + 0x98 + ((n) * 0x20)) argument
37 #define INTC_PENDING_FIQ(hw_base, n) REG32((hw_base) + 0x9c + ((n) * 0x20)) argument
38 #define INTC_ILR(hw_base, n) REG32((hw_base) + 0x100 + ((n) * 0x04)) argument
A Dgic.c37 #define GIC_DIST_IGROUP(hw_base, n) __REG32((hw_base) + 0x080 + ((n)/32) * 4) argument
38 #define GIC_DIST_ENABLE_SET(hw_base, n) __REG32((hw_base) + 0x100 + ((n)/32) * 4) argument
39 #define GIC_DIST_ENABLE_CLEAR(hw_base, n) __REG32((hw_base) + 0x180 + ((n)/32) * 4) argument
40 #define GIC_DIST_PENDING_SET(hw_base, n) __REG32((hw_base) + 0x200 + ((n)/32) * 4) argument
41 #define GIC_DIST_PENDING_CLEAR(hw_base, n) __REG32((hw_base) + 0x280 + ((n)/32) * 4) argument
42 #define GIC_DIST_ACTIVE_SET(hw_base, n) __REG32((hw_base) + 0x300 + ((n)/32) * 4) argument
43 #define GIC_DIST_ACTIVE_CLEAR(hw_base, n) __REG32((hw_base) + 0x380 + ((n)/32) * 4) argument
44 #define GIC_DIST_PRI(hw_base, n) __REG32((hw_base) + 0x400 + ((n)/4) * 4) argument
45 #define GIC_DIST_TARGET(hw_base, n) __REG32((hw_base) + 0x800 + ((n)/4) * 4) argument
46 #define GIC_DIST_CONFIG(hw_base, n) __REG32((hw_base) + 0xc00 + ((n)/16) * 4) argument
[all …]
/libcpu/arm/cortex-a/
A Dgicv3.h90 #define GIC_DIST_IGROUP(hw_base, n) __REG32((hw_base) + 0x080U + ((n)/32U) * 4U) argument
91 #define GIC_DIST_ENABLE_SET(hw_base, n) __REG32((hw_base) + 0x100U + ((n)/32U) * 4U) argument
92 #define GIC_DIST_ENABLE_CLEAR(hw_base, n) __REG32((hw_base) + 0x180U + ((n)/32U) * 4U) argument
93 #define GIC_DIST_PENDING_SET(hw_base, n) __REG32((hw_base) + 0x200U + ((n)/32U) * 4U) argument
94 #define GIC_DIST_PENDING_CLEAR(hw_base, n) __REG32((hw_base) + 0x280U + ((n)/32U) * 4U) argument
97 #define GIC_DIST_PRI(hw_base, n) __REG32((hw_base) + 0x400U + ((n)/4U) * 4U) argument
98 #define GIC_DIST_TARGET(hw_base, n) __REG32((hw_base) + 0x800U + ((n)/4U) * 4U) argument
101 #define GIC_DIST_CPENDSGI(hw_base, n) __REG32((hw_base) + 0xf10U + ((n)/4U) * 4U) argument
102 #define GIC_DIST_SPENDSGI(hw_base, n) __REG32((hw_base) + 0xf20U + ((n)/4U) * 4U) argument
104 #define GIC_DIST_IROUTER_LOW(hw_base, n) __REG32((hw_base) + 0x6000U + (n)*8U) argument
[all …]
A Dgic.c46 #define GIC_DIST_IGROUP(hw_base, n) __REG32((hw_base) + 0x080U + ((n)/32U) * 4U) argument
47 #define GIC_DIST_ENABLE_SET(hw_base, n) __REG32((hw_base) + 0x100U + ((n)/32U) * 4U) argument
48 #define GIC_DIST_ENABLE_CLEAR(hw_base, n) __REG32((hw_base) + 0x180U + ((n)/32U) * 4U) argument
49 #define GIC_DIST_PENDING_SET(hw_base, n) __REG32((hw_base) + 0x200U + ((n)/32U) * 4U) argument
50 #define GIC_DIST_PENDING_CLEAR(hw_base, n) __REG32((hw_base) + 0x280U + ((n)/32U) * 4U) argument
51 #define GIC_DIST_ACTIVE_SET(hw_base, n) __REG32((hw_base) + 0x300U + ((n)/32U) * 4U) argument
52 #define GIC_DIST_ACTIVE_CLEAR(hw_base, n) __REG32((hw_base) + 0x380U + ((n)/32U) * 4U) argument
53 #define GIC_DIST_PRI(hw_base, n) __REG32((hw_base) + 0x400U + ((n)/4U) * 4U) argument
54 #define GIC_DIST_TARGET(hw_base, n) __REG32((hw_base) + 0x800U + ((n)/4U) * 4U) argument
57 #define GIC_DIST_CPENDSGI(hw_base, n) __REG32((hw_base) + 0xf10U + ((n)/4U) * 4U) argument
[all …]
/libcpu/arm/cortex-r52/
A Dgicv3.h90 #define GIC_DIST_IGROUP(hw_base, n) __REG32((hw_base) + 0x080U + ((n)/32U) * 4U) argument
91 #define GIC_DIST_ENABLE_SET(hw_base, n) __REG32((hw_base) + 0x100U + ((n)/32U) * 4U) argument
92 #define GIC_DIST_ENABLE_CLEAR(hw_base, n) __REG32((hw_base) + 0x180U + ((n)/32U) * 4U) argument
93 #define GIC_DIST_PENDING_SET(hw_base, n) __REG32((hw_base) + 0x200U + ((n)/32U) * 4U) argument
94 #define GIC_DIST_PENDING_CLEAR(hw_base, n) __REG32((hw_base) + 0x280U + ((n)/32U) * 4U) argument
97 #define GIC_DIST_PRI(hw_base, n) __REG32((hw_base) + 0x400U + ((n)/4U) * 4U) argument
98 #define GIC_DIST_TARGET(hw_base, n) __REG32((hw_base) + 0x800U + ((n)/4U) * 4U) argument
101 #define GIC_DIST_CPENDSGI(hw_base, n) __REG32((hw_base) + 0xf10U + ((n)/4U) * 4U) argument
102 #define GIC_DIST_SPENDSGI(hw_base, n) __REG32((hw_base) + 0xf20U + ((n)/4U) * 4U) argument
104 #define GIC_DIST_IROUTER_LOW(hw_base, n) __REG32((hw_base) + 0x6000U + (n)*8U) argument
[all …]
/libcpu/arm/am335x/
A Dinterrupt.h32 #define INTC_SCR(hw_base, n) REG32((hw_base) + 0x70 + ((n) * 0x04)) argument
33 #define INTC_ITR(hw_base, n) REG32((hw_base) + 0x80 + ((n) * 0x20)) argument
34 #define INTC_MIR(hw_base, n) REG32((hw_base) + 0x84 + ((n) * 0x20)) argument
35 #define INTC_MIR_CLEAR(hw_base, n) REG32((hw_base) + 0x88 + ((n) * 0x20)) argument
36 #define INTC_MIR_SET(hw_base, n) REG32((hw_base) + 0x8c + ((n) * 0x20)) argument
37 #define INTC_ISR_SET(hw_base, n) REG32((hw_base) + 0x90 + ((n) * 0x20)) argument
38 #define INTC_ISR_CLEAR(hw_base, n) REG32((hw_base) + 0x94 + ((n) * 0x20)) argument
39 #define INTC_PENDING_IRQ(hw_base, n) REG32((hw_base) + 0x98 + ((n) * 0x20)) argument
40 #define INTC_PENDING_FIQ(hw_base, n) REG32((hw_base) + 0x9c + ((n) * 0x20)) argument
41 #define INTC_ILR(hw_base, n) REG32((hw_base) + 0x100 + ((n) * 0x04)) argument
A Dam33xx.h154 #define TPCC_MUX(n) 0xF90 + ((n) * 4) argument
220 #define DMTIMER_TCAR(base, n) REG32(base + 0x50 + (((n) - 1) * 8)) argument
/libcpu/aarch64/common/include/
A Dgicv3.h89 #define GIC_DIST_IGROUP(hw_base, n) HWREG32((hw_base) + 0x080U + ((n) / 32U) * 4U) argument
90 #define GIC_DIST_ENABLE_SET(hw_base, n) HWREG32((hw_base) + 0x100U + ((n) / 32U) * 4U) argument
91 #define GIC_DIST_ENABLE_CLEAR(hw_base, n) HWREG32((hw_base) + 0x180U + ((n) / 32U) * 4U) argument
92 #define GIC_DIST_PENDING_SET(hw_base, n) HWREG32((hw_base) + 0x200U + ((n) / 32U) * 4U) argument
93 #define GIC_DIST_PENDING_CLEAR(hw_base, n) HWREG32((hw_base) + 0x280U + ((n) / 32U) * 4U) argument
94 #define GIC_DIST_ACTIVE_SET(hw_base, n) HWREG32((hw_base) + 0x300U + ((n) / 32U) * 4U) argument
96 #define GIC_DIST_PRI(hw_base, n) HWREG32((hw_base) + 0x400U + ((n) / 4U) * 4U) argument
97 #define GIC_DIST_TARGET(hw_base, n) HWREG32((hw_base) + 0x800U + ((n) / 4U) * 4U) argument
100 #define GIC_DIST_CPENDSGI(hw_base, n) HWREG32((hw_base) + 0xf10U + ((n) / 4U) * 4U) argument
101 #define GIC_DIST_SPENDSGI(hw_base, n) HWREG32((hw_base) + 0xf20U + ((n) / 4U) * 4U) argument
[all …]
A Dpsci.h22 #define PSCI_0_2_FN(n) (PSCI_0_2_FN_BASE + (n)) argument
26 #define PSCI_0_2_FN64(n) (PSCI_0_2_FN64_BASE + (n)) argument
/libcpu/arm/zynqmp-r5/
A Dgic.c38 #define GIC_DIST_IGROUP(hw_base, n) __REG32((hw_base) + 0x080 + ((n)/32) * 4) argument
39 #define GIC_DIST_ENABLE_SET(hw_base, n) __REG32((hw_base) + 0x100 + ((n)/32) * 4) argument
40 #define GIC_DIST_ENABLE_CLEAR(hw_base, n) __REG32((hw_base) + 0x180 + ((n)/32) * 4) argument
41 #define GIC_DIST_PENDING_SET(hw_base, n) __REG32((hw_base) + 0x200 + ((n)/32) * 4) argument
42 #define GIC_DIST_PENDING_CLEAR(hw_base, n) __REG32((hw_base) + 0x280 + ((n)/32) * 4) argument
43 #define GIC_DIST_ACTIVE_SET(hw_base, n) __REG32((hw_base) + 0x300 + ((n)/32) * 4) argument
44 #define GIC_DIST_PRI(hw_base, n) __REG32((hw_base) + 0x400 + ((n)/4) * 4) argument
45 #define GIC_DIST_TARGET(hw_base, n) __REG32((hw_base) + 0x800 + ((n)/4) * 4) argument
46 #define GIC_DIST_CONFIG(hw_base, n) __REG32((hw_base) + 0xc00 + ((n)/16) * 4) argument
/libcpu/ppc/ppc405/
A Dstart_gcc.S36 #define SAVE_GPR(n, base) stw n,GPR0+4*(n)(base) argument
37 #define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base) argument
38 #define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base) argument
39 #define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base) argument
40 #define SAVE_10GPRS(n,base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base) argument
41 #define REST_GPR(n, base) lwz n,GPR0+4*(n)(base) argument
42 #define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base) argument
43 #define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base) argument
44 #define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base) argument
45 #define REST_10GPRS(n,base) REST_8GPRS(n, base); REST_2GPRS(n+8, base) argument
[all …]
/libcpu/mips/gs232/
A Dinterrupt.c139 rt_uint32_t intstatus, irq, n; in rt_do_mips_cpu_irq() local
144 n = ip - 2; in rt_do_mips_cpu_irq()
146 intstatus = (gs232_hw0_icregs+n)->int_isr & (gs232_hw0_icregs+n)->int_en; in rt_do_mips_cpu_irq()
151 gs232_do_IRQ((n<<5) + irq); in rt_do_mips_cpu_irq()
154 (gs232_hw0_icregs+n)->int_clr |= (1 << irq); in rt_do_mips_cpu_irq()
A Dmipscfg.c24 static rt_uint16_t m_pow(rt_uint16_t b, rt_uint16_t n) in m_pow() argument
28 while (n--) in m_pow()
/libcpu/aarch64/common/
A Dgic.c48 #define GIC_DIST_IGROUP(hw_base, n) __REG32((hw_base) + 0x080U + ((n)/32U) * 4U) argument
49 #define GIC_DIST_ENABLE_SET(hw_base, n) __REG32((hw_base) + 0x100U + ((n)/32U) * 4U) argument
50 #define GIC_DIST_ENABLE_CLEAR(hw_base, n) __REG32((hw_base) + 0x180U + ((n)/32U) * 4U) argument
51 #define GIC_DIST_PENDING_SET(hw_base, n) __REG32((hw_base) + 0x200U + ((n)/32U) * 4U) argument
52 #define GIC_DIST_PENDING_CLEAR(hw_base, n) __REG32((hw_base) + 0x280U + ((n)/32U) * 4U) argument
53 #define GIC_DIST_ACTIVE_SET(hw_base, n) __REG32((hw_base) + 0x300U + ((n)/32U) * 4U) argument
54 #define GIC_DIST_ACTIVE_CLEAR(hw_base, n) __REG32((hw_base) + 0x380U + ((n)/32U) * 4U) argument
55 #define GIC_DIST_PRI(hw_base, n) __REG32((hw_base) + 0x400U + ((n)/4U) * 4U) argument
56 #define GIC_DIST_TARGET(hw_base, n) __REG32((hw_base) + 0x800U + ((n)/4U) * 4U) argument
59 #define GIC_DIST_CPENDSGI(hw_base, n) __REG32((hw_base) + 0xf10U + ((n)/4U) * 4U) argument
[all …]
/libcpu/
A DKconfig10 default n
14 default n
21 default n
25 default n
29 default n
125 default n
185 default n
190 default n
301 default n
305 default n
[all …]
/libcpu/mips/common/
A Dexception.c83 exception_func_t rt_set_except_vector(int n, exception_func_t func) in rt_set_except_vector() argument
87 if ((n < 0) || (n >= RT_EXCEPTION_MAX) || (!func)) in rt_set_except_vector()
92 old_handler = sys_exception_handlers[n]; in rt_set_except_vector()
93 sys_exception_handlers[n] = func; in rt_set_except_vector()
A DKconfig5 default n
A Dexception.h23 exception_func_t rt_set_except_vector(int n, exception_func_t func);
/libcpu/arm/s3c24x0/
A Drtc.c23 #define BCD2BIN(n) (((((n) >> 4) & 0x0F) * 10) + ((n) & 0x0F)) argument
24 #define BIN2BCD(n) ((((n) / 10) << 4) | ((n) % 10)) argument
/libcpu/arm/AT91SAM7S/
A DAT91SAM7S.h73 #define AT91C_UDP_CSR(n) (*(&AT91C_UDP_CSR0 + n)) argument
75 #define AT91C_UDP_FDR(n) (*(&AT91C_UDP_FDR0 + n)) argument
96 #define AT91C_AIC_SMR(n) (*(&AT91C_AIC_SMR0 + n)) argument
98 #define AT91C_AIC_SVR(n) (*(&AT91C_AIC_SVR0 + n)) argument
/libcpu/mips/gs264/
A Dmipscfg.c26 static rt_uint16_t m_pow(rt_uint16_t b, rt_uint16_t n) in m_pow() argument
30 while (n--) in m_pow()
A Dmmu.c265 int n = 0; in find_vaddr() local
288 n = 0; in find_vaddr()
292 if (!n) in find_vaddr()
297 n++; in find_vaddr()
298 if (n >= pages) in find_vaddr()
307 if (!n) in find_vaddr()
312 n += (ARCH_SECTION_SIZE/ARCH_PAGE_SIZE); in find_vaddr()
313 if (n >= pages) in find_vaddr()
/libcpu/ppc/ppc405/include/asm/
A Dppc405.h916 #define SDR0_CUST0_NDFC_BP_ENCODE(n) ((((unsigned long)(n))&0xF)<<24) argument
917 #define SDR0_CUST0_NDFC_BP_DECODE(n) ((((unsigned long)(n))>>24)&0x0F) argument
920 #define SDR0_CUST0_NDFC_BAC_ENCODE(n) ((((unsigned long)(n))&0x3)<<22) argument
921 #define SDR0_CUST0_NDFC_BAC_DECODE(n) ((((unsigned long)(n))>>22)&0x03) argument
932 #define SDR0_CUST0_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFF)<<4) argument
933 #define SDR0_CUST0_NDRSC_DECODE(n) ((((unsigned long)(n))>>4)&0xFFF) argument
A Dprocessor.h1018 #define _GLOBAL(n)\ argument
1019 .globl n;\
1020 n:
1072 #define CPU_TYPE_ENTRY(n, v) \ argument
1073 { .name = #n, .soc_ver = SVR_##v, }
/libcpu/aarch64/
A DKconfig18 default n

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