Searched refs:out (Results 1 – 10 of 10) sorted by relevance
| /libcpu/arm/sep4020/ |
| A D | cpu.c | 152 * reset cpu by dog's time-out in cp15_rd()
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| /libcpu/aarch64/cortex-a/ |
| A D | entry_point.S | 48 .macro get_pvoff, tmp, out
50 get_phy \out, .boot_cpu_stack_top
51 sub \out, \out, \tmp
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| /libcpu/arm/cortex-r52/ |
| A D | start_iar.S | 258 ;@ Disable out-of-order single-precision floating point
278 ;@ Disable out-of-order completion for divide instructions in
286 orr r0, r0, #0x80 ;@ Set BIT 7 (Disable out-of-order completion
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| A D | start_gcc.S | 424 @ Disable out-of-order single-precision floating point
444 @ Disable out-of-order completion for divide instructions in
452 orr r0, r0, #0x80 @ Set BIT 7 (Disable out-of-order completion
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| A D | cp15_gcc.S | 64 add r2, r10, r10, lsr #1 @ work out 3x current cache level
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| /libcpu/aarch64/common/include/ |
| A D | gicv3.h | 28 #define GET_GICV3_REG(reg, out) __asm__ volatile ("mrs %0, " reg:"=r"(out)::"memory"); argument
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| /libcpu/arm/cortex-a/ |
| A D | start_gcc.S | 37 .macro get_pvoff, tmp, out
39 adr \out, _reset
40 sub \out, \out, \tmp
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| /libcpu/arm/cortex-r4/ |
| A D | start_ccs.asm | 443 ; Disable out-of-order single-precision floating point
466 ; Disable out-of-order completion for divide instructions in
476 orr r0, r0, #0x80 ; Set BIT 7 (Disable out-of-order completion
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| A D | start_gcc.S | 426 @ Disable out-of-order single-precision floating point
446 @ Disable out-of-order completion for divide instructions in
454 orr r0, r0, #0x80 @ Set BIT 7 (Disable out-of-order completion
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| /libcpu/ti-dsp/c28x/ |
| A D | context.s | 191 ; mask out non-critical interrupts and enable global interrupt
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