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Searched refs:priority (Results 1 – 25 of 37) sorted by relevance

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/libcpu/avr32/uc3/
A Dexception_gcc.S194 .irp priority, 0, 1, 2, 3
195 .global _int\priority
196 .type _int\priority, @function
197 _int\priority:
212 … mov r12, \priority // Pass the int_level parameter to the _get_interrupt_handler function.
215 …breq _spint\priority // If this was not a spurious interrupt (R12 != NULL), jump to the handl…
223 brne _spint\priority
228 _spint\priority:
238 breq spint\priority
245 spint\priority:
/libcpu/arm/cortex-r52/
A Dinterrupt.c185 void rt_hw_interrupt_set_priority(int vector, unsigned int priority) in rt_hw_interrupt_set_priority() argument
187 arm_gic_set_priority(0, vector, priority); in rt_hw_interrupt_set_priority()
204 void rt_hw_interrupt_set_priority_mask(unsigned int priority) in rt_hw_interrupt_set_priority_mask() argument
206 arm_gic_set_interface_prior_mask(0, priority); in rt_hw_interrupt_set_priority_mask()
A Dinterrupt.h41 void rt_hw_interrupt_set_priority(int vector, unsigned int priority);
44 void rt_hw_interrupt_set_priority_mask(unsigned int priority);
A Dgicv3.c258 void arm_gic_set_priority(rt_uint32_t index, int irq, rt_uint32_t priority) in arm_gic_set_priority() argument
274 mask |= ((priority & 0xFFUL) << ((irq % 4U) * 8U)); in arm_gic_set_priority()
281 mask |= ((priority & 0xFFUL) << ((irq % 4U) * 8U)); in arm_gic_set_priority()
327 void arm_gic_set_interface_prior_mask(rt_uint32_t index, rt_uint32_t priority) in arm_gic_set_interface_prior_mask() argument
331 priority &= 0xFFUL; in arm_gic_set_interface_prior_mask()
333 __set_gicv3_reg(ICC_PMR, priority); in arm_gic_set_interface_prior_mask()
339 rt_uint32_t priority; in arm_gic_get_interface_prior_mask() local
341 __get_gicv3_reg(ICC_PMR, priority); in arm_gic_get_interface_prior_mask()
342 return priority; in arm_gic_get_interface_prior_mask()
/libcpu/arm/cortex-a/
A Dinterrupt.h43 void rt_hw_interrupt_set_priority(int vector, unsigned int priority);
46 void rt_hw_interrupt_set_priority_mask(unsigned int priority);
A Dinterrupt.c227 void rt_hw_interrupt_set_priority(int vector, unsigned int priority) in rt_hw_interrupt_set_priority() argument
229 arm_gic_set_priority(0, vector, priority); in rt_hw_interrupt_set_priority()
246 void rt_hw_interrupt_set_priority_mask(unsigned int priority) in rt_hw_interrupt_set_priority_mask() argument
248 arm_gic_set_interface_prior_mask(0, priority); in rt_hw_interrupt_set_priority_mask()
A Dgic.h35 void arm_gic_set_priority(rt_uint32_t index, int irq, rt_uint32_t priority);
38 void arm_gic_set_interface_prior_mask(rt_uint32_t index, rt_uint32_t priority);
A Dgicv3.c259 void arm_gic_set_priority(rt_uint32_t index, int irq, rt_uint32_t priority) in arm_gic_set_priority() argument
275 mask |= ((priority & 0xFFUL) << ((irq % 4U) * 8U)); in arm_gic_set_priority()
282 mask |= ((priority & 0xFFUL) << ((irq % 4U) * 8U)); in arm_gic_set_priority()
327 void arm_gic_set_interface_prior_mask(rt_uint32_t index, rt_uint32_t priority) in arm_gic_set_interface_prior_mask() argument
331 priority &= 0xFFUL; in arm_gic_set_interface_prior_mask()
333 __set_gicv3_reg(ICC_PMR, priority); in arm_gic_set_interface_prior_mask()
339 rt_uint32_t priority; in arm_gic_get_interface_prior_mask() local
341 __get_gicv3_reg(ICC_PMR, priority); in arm_gic_get_interface_prior_mask()
342 return priority; in arm_gic_get_interface_prior_mask()
/libcpu/aarch64/common/include/
A Dinterrupt.h43 void rt_hw_interrupt_set_priority(int vector, unsigned int priority);
46 void rt_hw_interrupt_set_priority_mask(unsigned int priority);
A Dgic.h35 void arm_gic_set_priority(rt_uint64_t index, int irq, rt_uint64_t priority);
38 void arm_gic_set_interface_prior_mask(rt_uint64_t index, rt_uint64_t priority);
/libcpu/arm/cortex-m4/
A DREADME.md41 int "Set max syscall interrupt priority"
47 - Select `RT_MAX_SYSCALL_INTERRUPT_PRIORITY` to set the maximum priority of the interrupt that can …
51 …ERRUPT_PRIORITY` is set to 0x01, the system masking only interrupts with a priority of `0x01-0xFF`.
52 - Interrupts with a priority of 0 are not managed by the system and can continue to respond to inte…
53 …ister for independent interrupt management, note that interrupts with a priority value lower than …
A Dcontext_iar.S24 NVIC_SYSPRI2 EQU 0xE000ED20 ; system priority register (2)
25 NVIC_PENDSV_PRI EQU 0xFFFF0000 ; PendSV and SysTick priority value (lowest)
192 ; set the PendSV and SysTick exception priority
214 ; clear the BASEPRI register to disable masking priority
A Dcontext_rvds.S23 NVIC_SYSPRI2 EQU 0xE000ED20 ; system priority register (2)
24 NVIC_PENDSV_PRI EQU 0xFFFF0000 ; PendSV and SysTick priority value (lowest)
190 ; set the PendSV and SysTick exception priority
212 ; clear the BASEPRI register to disable masking priority
/libcpu/risc-v/virt64/
A Dplic.c42 void plic_set_priority(int irq, int priority) in plic_set_priority() argument
44 *(uint32_t *)PLIC_PRIORITY(irq) = priority; in plic_set_priority()
A Dplic.h68 void plic_set_priority(int irq, int priority);
/libcpu/aarch64/common/
A Dinterrupt.c277 void rt_hw_interrupt_set_priority(int vector, unsigned int priority) in rt_hw_interrupt_set_priority() argument
279 arm_gic_set_priority(0, vector, priority); in rt_hw_interrupt_set_priority()
296 void rt_hw_interrupt_set_priority_mask(unsigned int priority) in rt_hw_interrupt_set_priority_mask() argument
298 arm_gic_set_interface_prior_mask(0, priority); in rt_hw_interrupt_set_priority_mask()
A Dgicv3.c271 void arm_gic_set_priority(rt_uint64_t index, int irq, rt_uint64_t priority) in arm_gic_set_priority() argument
286 mask |= ((priority & 0xff) << ((irq % 4) * 8)); in arm_gic_set_priority()
293 mask |= ((priority & 0xff) << ((irq % 4) * 8)); in arm_gic_set_priority()
336 void arm_gic_set_interface_prior_mask(rt_uint64_t index, rt_uint64_t priority) in arm_gic_set_interface_prior_mask() argument
340 priority &= 0xff; in arm_gic_set_interface_prior_mask()
342 SET_GICV3_REG(ICC_PMR_EL1, priority); in arm_gic_set_interface_prior_mask()
348 rt_uint64_t priority; in arm_gic_get_interface_prior_mask() local
350 GET_GICV3_REG(ICC_PMR_EL1, priority); in arm_gic_get_interface_prior_mask()
351 return priority; in arm_gic_get_interface_prior_mask()
/libcpu/arm/am335x/
A Dinterrupt.c123 void rt_hw_interrupt_control(int vector, int priority, int route) in rt_hw_interrupt_control() argument
132 INTC_ILR(AINTC_BASE, vector) = ((priority << 0x02) & 0x1FC) | fiq ; in rt_hw_interrupt_control()
/libcpu/c-sky/ck802/
A Dcore_ck802.c189 void drv_nvic_set_prio(int32_t IRQn, uint32_t priority) in drv_nvic_set_prio() argument
192 … (((priority << (8U - s_nvic_prio_bits)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); in drv_nvic_set_prio()
/libcpu/c-sky/common/
A Dcsi_core.h96 void drv_nvic_set_prio(int32_t irq_num, uint32_t priority);
/libcpu/arm/cortex-m3/
A Dcontext_iar.S21 NVIC_SYSPRI2 EQU 0xE000ED20 ; system priority register (2)
22 NVIC_PENDSV_PRI EQU 0xFFFF0000 ; PendSV and SysTick priority value (lowest)
142 ; set the PendSV and SysTick exception priority
A Dcontext_rvds.S20 NVIC_SYSPRI2 EQU 0xE000ED20 ; system priority register (2)
21 NVIC_PENDSV_PRI EQU 0xFFFF0000 ; PendSV and SysTick priority value (lowest)
148 ; set the PendSV and SysTick exception priority
/libcpu/arm/cortex-m0/
A Dcontext_iar.S21 NVIC_SHPR3 EQU 0xE000ED20 ; system priority register (2)
22 NVIC_PENDSV_PRI EQU 0xFFFF0000 ; PendSV and SysTick priority value (lowest)
166 ; set the PendSV and SysTick exception priority
A Dcontext_rvds.S21 NVIC_SHPR3 EQU 0xE000ED20 ; system priority register (2)
22 NVIC_PENDSV_PRI EQU 0xFFFF0000 ; PendSV and SysTick priority value (lowest)
171 ; set the PendSV and SysTick exception priority
/libcpu/arm/cortex-m23/
A Dcontext_iar.S22 NVIC_SHPR3 EQU 0xE000ED20 ; system priority register (2)
23 NVIC_PENDSV_PRI EQU 0xFFFF0000 ; PendSV and SysTick priority value (lowest)
167 ; set the PendSV and SysTick exception priority

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