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Searched refs:pte (Results 1 – 6 of 6) sorted by relevance

/libcpu/risc-v/common64/
A Dmmu.h43 #define GET_PPN(pte) \ argument
44 (__PARTBIT(pte, PTE_PPN_SHIFT, PHYSICAL_ADDRESS_WIDTH_BITS - PAGE_OFFSET_BIT))
45 #define GET_PADDR(pte) (GET_PPN(pte) << PAGE_OFFSET_BIT) argument
A Dmmu.c512 rt_ubase_t *pte = _query(aspace, vaddr, &level); in rt_hw_mmu_v2p() local
515 if (pte) in rt_hw_mmu_v2p()
517 paddr = GET_PADDR(*pte); in rt_hw_mmu_v2p()
528 static int _noncache(rt_base_t *pte) in _noncache() argument
533 static int _cache(rt_base_t *pte) in _cache() argument
538 static int (*control_handler[MMU_CNTL_DUMMY_END])(rt_base_t *pte)=
568 int (*handler)(rt_base_t *pte); in rt_hw_mmu_control()
575 rt_base_t *pte = _query(aspace, vaddr, &level); in rt_hw_mmu_control() local
579 if (pte) in rt_hw_mmu_control()
581 err = handler(pte); in rt_hw_mmu_control()
/libcpu/risc-v/virt64/
A Driscv_mmu.h59 #define PAGE_IS_LEAF(pte) __MASKVALUE(pte, PAGE_ATTR_RWX) argument
61 #define PTE_USED(pte) __MASKVALUE(pte, PTE_V) argument
/libcpu/risc-v/t-head/c908/
A Driscv_mmu.h70 #define PAGE_IS_LEAF(pte) __MASKVALUE(pte, PAGE_ATTR_RWX) argument
72 #define PTE_USED(pte) __MASKVALUE(pte, PTE_V) argument
/libcpu/aarch64/common/
A Dmmu.c817 unsigned long *pte = _query(aspace, v_addr, &level_shift); in rt_hw_mmu_v2p() local
819 if (pte) in rt_hw_mmu_v2p()
821 paddr = *pte & MMU_ADDRESS_MASK; in rt_hw_mmu_v2p()
833 static int _noncache(rt_ubase_t *pte) in _noncache() argument
838 rt_ubase_t entry = *pte; in _noncache()
851 static int _cache(rt_ubase_t *pte) in _cache() argument
856 rt_ubase_t entry = *pte; in _cache()
859 *pte = (entry & ~idx_mask) | (NORMAL_MEM << idx_shift); in _cache()
882 int (*handler)(rt_ubase_t * pte); in rt_hw_mmu_control()
893 if (pte) in rt_hw_mmu_control()
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/libcpu/risc-v/t-head/c906/
A Driscv_mmu.h74 #define PAGE_IS_LEAF(pte) __MASKVALUE(pte, PAGE_ATTR_RWX) argument
76 #define PTE_USED(pte) __MASKVALUE(pte, PTE_V) argument

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