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Searched refs:r3 (Results 1 – 25 of 112) sorted by relevance

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/libcpu/ppc/ppc405/
A Ddcr_gcc.S62 rlwinm r3, r3, 5, 22, 26
63 or r3, r3, r0
64 slwi r3, r3, 10
65 oris r3, r3, 0x3e30 /* RT = %r3 */
66 ori r3, r3, 323 /* XO = 323 */
67 slwi r3, r3, 1 /* CR = 0 */
107 rlwinm r3, r3, 5, 22, 26
108 or r3, r3, r0
109 slwi r3, r3, 10
111 ori r3, r3, 451 /* XO = 451 */
[all …]
A Dcache_gcc.S23 andc r3,r3,r5
29 mr r6,r3
31 addi r3,r3,L1_CACHE_BYTES
52 andc r3,r3,r5
60 addi r3,r3,L1_CACHE_BYTES
74 andc r3,r3,r5
82 addi r3,r3,L1_CACHE_BYTES
97 andc r3,r3,r5
105 addi r3,r3,L1_CACHE_BYTES
171 srwi r3, r3, 31 /* >>31 => select bit 0 */
[all …]
A Dcontext_gcc.S21 andc r4,r4,r3
30 mfmsr r3
41 mtmsr r3
57 ori r3,r3,rt_thread_switch_interrput_flag@l
58 lwz r4,0(r3)
62 stw r4,0(r3)
66 ori r3,r3,rt_interrupt_from_thread@l
67 lwz r3,0(r3)
74 stw r1, 0(r3)
77 mfspr r3,SPRG0
[all …]
A Dstart_gcc.S275 addi r3,r1,STACK_FRAME_OVERHEAD
289 addi r3,r1,STACK_FRAME_OVERHEAD
416 ori r3,r3, 0xFFFF
417 mtdcr dmasr, r3
420 lis r3,START_BSS@h // load start of BSS into r3
421 ori r3,r3,START_BSS@l
424 sub r4,r4,r3 // calculate length of BSS
429 subi r3,r3,4 // because of offset start 4 bytes lower
432 stwu r5,4(r3) // zero one word of BSS section
494 addi r3,r1,STACK_FRAME_OVERHEAD
[all …]
/libcpu/xilinx/microblaze/
A Dcontext_gcc.S29 MFS r3, RMSR
75 ANDI r3, r3, IE_BIT
79 MTS RMSR,r3
89 MTS RMSR,r3
131 SWI r4, r3, 0
152 ORI r3, r3, IE_BIT
169 LWI r4, r3, 0
175 ANDNI r3, r3, IE_BIT
190 LW r4, r0, r3
194 LW r4, r0, r3
[all …]
/libcpu/arm/common/
A Ddivsi3.S255 addhs r3, r3,r2, lsl #31
343 addhs r3, r3,r2, lsl #9
347 addhs r3, r3,r2, lsl #8
351 addhs r3, r3,r2, lsl #7
355 addhs r3, r3,r2, lsl #6
359 addhs r3, r3,r2, lsl #5
363 addhs r3, r3,r2, lsl #4
367 addhs r3, r3,r2, lsl #3
379 addhs r3, r3, r2
396 mov r3, r3, lsl #1
[all …]
/libcpu/arm/cortex-a/
A Dcontext_gcc.S156 push {r0 - r3, lr}
161 pop {r0 - r3, lr}
166 mov r0, r3
186 ldr r3, [ip]
187 cmp r3, #1
190 str r0, [r3]
192 str r3, [ip]
206 ldr r3, [ip]
207 cmp r3, #1
210 str r0, [r3]
[all …]
/libcpu/arc/em/
A Dcontex_gcc_mw.S183 mov r0, r3
257 add r2, r3, 1
285 lr r3, [AUX_IRQ_HINT]
286 cmp r3, r0
288 xor r3, r3, r3
289 sr r3, [AUX_IRQ_HINT]
309 bclr r2, r1, r3
357 lr r3, [AUX_IRQ_HINT]
358 cmp r3, r0
360 xor r3, r3, r3
[all …]
/libcpu/arm/lpc214x/
A Dstartup_gcc.S81 mov r3, #PLLCFG_Val
82 str r3, [r0, #PLLCFG_OFS]
83 mov r3, #PLLCON_PLLE
84 str r3, [r0, #PLLCON_OFS]
90 ldr r3, [r0, #PLLSTAT_OFS]
91 ands r3, r3, #PLLSTAT_PLOCK
95 mov r3, #(PLLCON_PLLE|PLLCON_PLLC)
96 str r3, [r0, #PLLCON_OFS]
148 str r0, [r3]
151 add r3, r3, #4
[all …]
A Dcontext_gcc.S96 LDR r3, [r2] /* 载入中断中切换标致地址 */
97 CMP r3, #1 /* 等于 1 ？*/
99 MOV r3, #1 /* set rt_thread_switch_interrupt_flag to 1*/
101 STR r3, [r2] /* */
/libcpu/arm/cortex-m33/
A Dcontext_gcc.S66 LDR r3, [r2]
67 CMP r3, #1
69 MOV r3, #1
70 STR r3, [r2]
132 MRS r3, psplim /* r3 = psplim */
156 MOV r3, lr /* r3 = lr */
173 MOV lr, r3 /* lr = r3 */
183 MOV lr, r3 /* lr = r1 */
198 PUSH {r0-r3, r12, lr}
201 POP {r0-r3, r12, lr}
[all …]
A Dcontext_iar.S67 LDR r3, [r2]
68 CMP r3, #1
70 MOV r3, #1
71 STR r3, [r2]
87 ; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack
132 MRS r3, psplim ; r3 = psplim
157 MOV r3, lr ; r3 = lr
175 MOV lr, r3 ; lr = r3
184 POP {r1, r3} ; pop lr, thread_stack
185 MOV lr, r3 ; lr = r1
[all …]
A Dcontext_rvds.S69 LDR r3, [r2]
70 CMP r3, #1
72 MOV r3, #1
73 STR r3, [r2]
90 ; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack
135 MRS r3, psplim ; r3 = psplim
158 MOV r3, lr ; r3 = lr
175 MOV lr, r3 ; lr = r3
184 POP {r1, r3} ; pop lr, thread_stack
185 MOV lr, r3 ; lr = r1
[all …]
/libcpu/unicore32/sep6200/
A Dcontext_gcc.S51 stm.w (r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r13, r14, r15), [sp-]
65 ldm.w (r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r13, r14, r15), [sp]+
79 ldm.w (r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r13, r14, r15), [sp]+
91 ldw r3, [r2+]
92 cmpsub.a r3, #1
94 mov r3, #1
95 stw r3, [r2+]
/libcpu/arm/lpc24xx/
A Dstart_gcc.S128 ldr r3, =_sdata /* sram data start */
131 str r0, [r3]
134 add r3, r3, #4
136 cmp r3, r2 /* check if data to clear */
220 stmfd sp!, {r0-r3} /* save r0-r3 */
225 mrs r3, spsr /* disable interrupt */
226 orr r0, r3, #NOINT
235 mov r5, r3
236 ldmfd r4!, {r0-r3}
237 stmfd sp!, {r0-r3} /* push old task's r3-r0 */
/libcpu/arm/cortex-m7/
A Dcontext_gcc.S66 LDR r3, [r2]
67 CMP r3, #1
69 MOV r3, #1
70 STR r3, [r2]
137 LDMFD r1!, {r3} /* pop flag */
143 CMP r3, #0 /* if(flag_r3 != 0) */
152 CMP r3, #0 /* if(flag_r3 != 0) */
158 PUSH {r0-r3, r12, lr}
161 POP {r0-r3, r12, lr}
/libcpu/arm/armv6/
A Darm_entry_gcc.S19 stmfd sp!, {r0-r3, ip, lr}
25 1: ldmfd sp!, {r0-r3, ip, lr}
31 stmfd sp!, {r0-r3, ip, lr}
38 1: ldmfd sp!, {r0-r3, ip, lr}
44 stmfd sp!, {r0-r3, ip, lr}
45 mov r3, \arg3
53 1: ldmfd sp!, {r0-r3, ip, lr}
/libcpu/arm/AT91SAM7X/
A Dstart_gcc.S154 ldr r3, =_sdata /* sram data start */
157 str r0, [r3]
160 add r3, r3, #4
162 cmp r3, r2 /* check if data to clear */
240 stmfd sp!, {r0-r3} @ save r0-r3
255 mov r5, r3
256 ldmfd r4!, {r0-r3}
257 stmfd sp!, {r0-r3} @ push old task's r3-r0
/libcpu/arm/AT91SAM7S/
A Dcontext_gcc.S80 ldr r3, [r2]
81 cmp r3, #1
83 mov r3, #1 /* set rt_thread_switch_interrupt_flag to 1 */
84 str r3, [r2]
A Dstart_gcc.S131 ldr r3, =_edata
133 cmp r2, r3
198 stmfd sp!, {r0-r3} /* save r0-r3 */
203 mrs r3, spsr /* disable interrupt */
204 orr r0, r3, #I_BIT|F_BIT
213 mov r5, r3
214 ldmfd r4!, {r0-r3}
215 stmfd sp!, {r0-r3} /* push old task's r3-r0 */
/libcpu/arm/cortex-r4/
A Dcontext_ccs.asm203 STMDB sp, {r0-r3} ; save r0-r3. We will restore r0-r3 in the SVC
205 SUB r1, sp, #16 ; save the right SP value in r1, so we could restore r0-r3.
216 STMDB sp!, {r4-r7} ; push old task's r3-r0. We don't need to push/pop them to
219 STMDB sp!, {r3} ; push old task's cpsr
A Dcontext_gcc.S197 STMDB sp, {r0-r3} @ save r0-r3. We will restore r0-r3 in the SVC
199 SUB r1, sp, #16 @ save the right SP value in r1, so we could restore r0-r3.
210 STMDB sp!, {r4-r7} @ push old task's r3-r0. We don't need to push/pop them to
213 STMDB sp!, {r3} @ push old task's cpsr
/libcpu/arm/cortex-r52/
A Dcontext_gcc.S194 STMDB sp, {r0-r3} @ save r0-r3. We will restore r0-r3 in the SVC
196 SUB r1, sp, #16 @ save the right SP value in r1, so we could restore r0-r3.
207 STMDB sp!, {r4-r7} @ push old task's r3-r0. We don't need to push/pop them to
210 STMDB sp!, {r3} @ push old task's cpsr
A Dcontext_iar.S202 STMDB sp, {r0-r3} ; save r0-r3. We will restore r0-r3 in the SVC
204 SUB r1, sp, #16 ; save the right SP value in r1, so we could restore r0-r3.
215 STMDB sp!, {r4-r7} ; push old task's r3-r0. We don't need to push/pop them to
218 STMDB sp!, {r3} ; push old task's cpsr
/libcpu/arm/cortex-m85/
A Dcontext_gcc.S64 LDR r3, [r2]
65 CMP r3, #1
67 MOV r3, #1
68 STR r3, [r2]
140 LDMFD r1!, {r3} /* pop flag */
146 CMP r3, #0 /* if(flag_r3 != 0) */
155 CMP r3, #0 /* if(flag_r3 != 0) */

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