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Searched refs:reg (Results 1 – 25 of 26) sorted by relevance

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/libcpu/aarch64/common/include/
A Dasm-fpu.h14 .macro SAVE_FPU, reg
15 str q0, [\reg, #-0x10]!
16 str q1, [\reg, #-0x10]!
17 str q2, [\reg, #-0x10]!
18 str q3, [\reg, #-0x10]!
19 str q4, [\reg, #-0x10]!
20 str q5, [\reg, #-0x10]!
21 str q6, [\reg, #-0x10]!
22 str q7, [\reg, #-0x10]!
23 str q8, [\reg, #-0x10]!
[all …]
A Dgicv3.h28 #define GET_GICV3_REG(reg, out) __asm__ volatile ("mrs %0, " reg:"=r"(out)::"memory"); argument
29 #define SET_GICV3_REG(reg, in) __asm__ volatile ("msr " reg ", %0"::"r"(in):"memory"); argument
/libcpu/risc-v/common/
A Driscv-ops.h16 #define read_csr(reg) ({ unsigned long __tmp; \ argument
17 asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
20 #define write_csr(reg, val) ({ \ argument
22 asm volatile ("csrw " #reg ", %0" :: "i"(val)); \
24 asm volatile ("csrw " #reg ", %0" :: "r"(val)); })
26 #define set_csr(reg, bit) ({ unsigned long __tmp; \ argument
28 asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
30 asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
33 #define clear_csr(reg, bit) ({ unsigned long __tmp; \ argument
35 asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
[all …]
/libcpu/arm/cortex-a/
A Dpmu.c18 unsigned long reg; in rt_hw_pmu_dump_feature() local
20 reg = rt_hw_pmu_get_control(); in rt_hw_pmu_dump_feature()
22 reg >> 24, (reg >> 16) & 0xff, (reg >> 11) & 0x1f); in rt_hw_pmu_dump_feature()
23 RT_ASSERT(ARM_PMU_CNTER_NR == ((reg >> 11) & 0x1f)); in rt_hw_pmu_dump_feature()
24 RT_UNUSED(reg); in rt_hw_pmu_dump_feature()
A Dpmu.h71 unsigned long reg; in rt_hw_pmu_get_ceid() local
73 asm ("mrc p15, 0, %0, c9, c12, 6" : "=r"(reg)); in rt_hw_pmu_get_ceid()
74 return reg; in rt_hw_pmu_get_ceid()
132 unsigned long reg; in rt_hw_pmu_read_counter() local
136 asm volatile ("mrc p15, 0, %0, c9, c13, 2" : "=r"(reg)); in rt_hw_pmu_read_counter()
137 return reg; in rt_hw_pmu_read_counter()
142 unsigned long reg; in rt_hw_pmu_get_ovsr() local
144 asm ("mrc p15, 0, %0, c9, c12, 3" : "=r"(reg)); in rt_hw_pmu_get_ovsr()
145 return reg; in rt_hw_pmu_get_ovsr()
148 rt_inline void rt_hw_pmu_clear_ovsr(unsigned long reg) in rt_hw_pmu_clear_ovsr() argument
[all …]
A Dbacktrace.c211 unsigned long **vsp, unsigned int reg) in unwind_pop_register() argument
217 ctrl->vrs[reg] = *(*vsp)++; in unwind_pop_register()
226 int load_sp, reg = 4; in unwind_exec_pop_subset_r4_to_r13() local
232 if (unwind_pop_register(ctrl, &vsp, reg)) in unwind_exec_pop_subset_r4_to_r13()
235 reg++; in unwind_exec_pop_subset_r4_to_r13()
247 int reg; in unwind_exec_pop_r4_to_rN() local
250 for (reg = 4; reg <= 4 + (insn & 7); reg++) in unwind_exec_pop_r4_to_rN()
251 if (unwind_pop_register(ctrl, &vsp, reg)) in unwind_exec_pop_r4_to_rN()
267 int reg = 0; in unwind_exec_pop_subset_r0_to_r3() local
273 if (unwind_pop_register(ctrl, &vsp, reg)) in unwind_exec_pop_subset_r0_to_r3()
[all …]
/libcpu/arm/s3c44b0/
A Dcpu.c25 rt_base_t reg; in rt_hw_cpu_icache_enable() local
45 reg = SYSCFG; in rt_hw_cpu_icache_enable()
46 reg |= 0x00000006; /* 8kB */ in rt_hw_cpu_icache_enable()
47 SYSCFG = reg; in rt_hw_cpu_icache_enable()
56 rt_base_t reg; in rt_hw_cpu_icache_disable() local
58 reg = SYSCFG; in rt_hw_cpu_icache_disable()
59 reg &= ~0x00000006; /* 8kB */ in rt_hw_cpu_icache_disable()
60 SYSCFG = reg; in rt_hw_cpu_icache_disable()
/libcpu/ppc/ppc405/include/asm/
A Dppc4xx.h78 #define mtcpr(reg, d) do { mtdcr(cprcfga,reg);mtdcr(cprcfgd,d); } while (0) argument
79 #define mfcpr(reg, d) do { mtdcr(cprcfga,reg);d = mfdcr(cprcfgd); } while (0) argument
81 #define mtebc(reg, d) do { mtdcr(ebccfga,reg);mtdcr(ebccfgd,d); } while (0) argument
82 #define mfebc(reg, d) do { mtdcr(ebccfga,reg);d = mfdcr(ebccfgd); } while (0) argument
84 #define mtsdram(reg, d) do { mtdcr(memcfga,reg);mtdcr(memcfgd,d); } while (0) argument
85 #define mfsdram(reg, d) do { mtdcr(memcfga,reg);d = mfdcr(memcfgd); } while (0) argument
87 #define mtsdr(reg, d) do { mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,d); } while (0) argument
88 #define mfsdr(reg, d) do { mtdcr(sdrcfga,reg);d = mfdcr(sdrcfgd); } while (0) argument
/libcpu/arm/realview-a8-vmm/
A Dpmu.c14 unsigned long reg; in rt_hw_pmu_dump_feature() local
16 reg = rt_hw_pmu_get_control(); in rt_hw_pmu_dump_feature()
18 reg >> 24, (reg >> 16) & 0xff, (reg >> 11) & 0x1f); in rt_hw_pmu_dump_feature()
19 RT_ASSERT(ARM_PMU_CNTER_NR == ((reg >> 11) & 0x1f)); in rt_hw_pmu_dump_feature()
A Dpmu.h71 unsigned long reg; in rt_hw_pmu_get_ceid() local
73 asm ("mrc p15, 0, %0, c9, c12, 6" : "=r"(reg)); in rt_hw_pmu_get_ceid()
74 return reg; in rt_hw_pmu_get_ceid()
132 unsigned long reg; in rt_hw_pmu_read_counter() local
136 asm volatile ("mrc p15, 0, %0, c9, c13, 2" : "=r"(reg)); in rt_hw_pmu_read_counter()
137 return reg; in rt_hw_pmu_read_counter()
142 unsigned long reg; in rt_hw_pmu_get_ovsr() local
144 asm ("mrc p15, 0, %0, c9, c12, 3" : "=r"(reg)); in rt_hw_pmu_get_ovsr()
145 return reg; in rt_hw_pmu_get_ovsr()
148 rt_inline void rt_hw_pmu_clear_ovsr(unsigned long reg) in rt_hw_pmu_clear_ovsr() argument
[all …]
A Dgic.c291 unsigned int reg; in arm_gic_trigger() local
296 reg = (target_cpu << 16) | irq; in arm_gic_trigger()
297 GIC_DIST_SOFTINT(_gic_table[index].dist_hw_base) = reg; in arm_gic_trigger()
/libcpu/arm/zynqmp-r5/
A Dxpseudo_asm_gcc.h211 #define mtcpdc(reg,val) __asm__ __volatile__("dc " #reg ",%0" : : "r" (val)) argument
212 #define mtcpic(reg,val) __asm__ __volatile__("ic " #reg ",%0" : : "r" (val)) argument
214 #define mtcpicall(reg) __asm__ __volatile__("ic " #reg) argument
215 #define mtcptlbi(reg) __asm__ __volatile__("tlbi " #reg) argument
216 #define mtcpat(reg,val) __asm__ __volatile__("at " #reg ",%0" : : "r" (val)) argument
218 #define mfcp(reg) ({u64 rval = 0U;\ argument
219 __asm__ __volatile__("mrs %0, " #reg : "=r" (rval));\
223 #define mtcp(reg,val) __asm__ __volatile__("msr " #reg ",%0" : : "r" (val)) argument
A Dgic.c197 unsigned int reg; in arm_gic_trigger() local
202 reg = (target_cpu << 16) | irq; in arm_gic_trigger()
203 GIC_DIST_SOFTINT(_gic_table[index].dist_hw_base) = reg; in arm_gic_trigger()
/libcpu/risc-v/t-head/c906/
A Dplic.c143 … uint32_t *reg = (uint32_t *)((rt_size_t)handler->enable_base + (hwirq / 32) * sizeof(uint32_t)); in plic_toggle() local
148 writel(readl(reg) | hwirq_mask, reg); in plic_toggle()
152 writel(readl(reg) & ~hwirq_mask, reg); in plic_toggle()
/libcpu/risc-v/t-head/c908/
A Dplic.c143 … uint32_t *reg = (uint32_t *)((rt_size_t)handler->enable_base + (hwirq / 32) * sizeof(uint32_t)); in plic_toggle() local
148 writel(readl(reg) | hwirq_mask, reg); in plic_toggle()
152 writel(readl(reg) & ~hwirq_mask, reg); in plic_toggle()
/libcpu/arm/cortex-r52/
A Dbacktrace.c212 unsigned long **vsp, unsigned int reg) in unwind_pop_register() argument
218 ctrl->vrs[reg] = *(*vsp)++; in unwind_pop_register()
227 int load_sp, reg = 4; in unwind_exec_pop_subset_r4_to_r13() local
233 if (unwind_pop_register(ctrl, &vsp, reg)) in unwind_exec_pop_subset_r4_to_r13()
236 reg++; in unwind_exec_pop_subset_r4_to_r13()
248 int reg; in unwind_exec_pop_r4_to_rN() local
251 for (reg = 4; reg <= 4 + (insn & 7); reg++) in unwind_exec_pop_r4_to_rN()
252 if (unwind_pop_register(ctrl, &vsp, reg)) in unwind_exec_pop_r4_to_rN()
268 int reg = 0; in unwind_exec_pop_subset_r0_to_r3() local
274 if (unwind_pop_register(ctrl, &vsp, reg)) in unwind_exec_pop_subset_r0_to_r3()
[all …]
/libcpu/mips/common/
A Dmips_regs.h750 #define __read_ulong_c0_register(reg, sel) \ argument
752 __read_32bit_c0_register(reg, sel) : \
753 __read_64bit_c0_register(reg, sel))
758 __write_32bit_c0_register(reg, sel, val); \
760 __write_64bit_c0_register(reg, sel, val); \
1136 #define readb(reg) (*((volatile unsigned char *) (reg))) argument
1137 #define readw(reg) (*((volatile unsigned short *) (reg))) argument
1138 #define readl(reg) (*((volatile unsigned int *) (reg))) argument
1140 #define writeb(data, reg) ((*((volatile unsigned char *)(reg))) = (unsigned char)(data)) argument
1141 #define writew(data, reg) ((*((volatile unsigned short *)(reg))) = (unsigned short)(data)) argument
[all …]
A Dexception.c105 int reg = 4 * i + j; in mips_dump_regs() local
106 rt_kprintf("%d: 0x%08x, ", reg, regs->regs[reg]); in mips_dump_regs()
/libcpu/risc-v/common64/
A Dcontext_gcc.S20 .macro SAVE_REG reg, index
21 STORE \reg, \index*REGBYTES(sp)
24 .macro LOAD_REG reg, index
25 LOAD \reg, \index*REGBYTES(sp)
A Dencoding.h203 #define read_csr(reg) ({ unsigned long __tmp; \ argument
204 asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
207 #define write_csr(reg, val) ({ \ argument
209 asm volatile ("csrw " #reg ", %0" :: "i"(val)); \
211 asm volatile ("csrw " #reg ", %0" :: "r"(val)); })
213 #define swap_csr(reg, val) ({ unsigned long __tmp; \ argument
215 asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "i"(val)); \
217 asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \
220 #define set_csr(reg, bit) ({ unsigned long __tmp; \ argument
222 asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
[all …]
/libcpu/xilinx/microblaze/
A Dtrap.c137 volatile u32 reg; /* used as bit bucket */ in rt_hw_trap_irq() local
184 reg = XIntc_GetIntrStatus(cfg_ptr->BaseAddress); in rt_hw_trap_irq()
/libcpu/aarch64/cortex-a/
A Dentry_point.S43 .macro get_phy, reg, symbol
44 adrp \reg, \symbol
45 add \reg, \reg, #:lo12:\symbol
/libcpu/unicore32/sep6200/
A Dsep6200.h407 #define write_reg(reg,value) \ argument
410 *(RP)(reg) = value; \
413 #define read_reg(reg) (*(RP)reg) argument
/libcpu/risc-v/rv64/
A Dencoding.h186 #define read_csr(reg) ({ unsigned long __tmp; \ argument
187 asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
190 #define write_csr(reg, val) ({ \ argument
192 asm volatile ("csrw " #reg ", %0" :: "i"(val)); \
194 asm volatile ("csrw " #reg ", %0" :: "r"(val)); })
196 #define swap_csr(reg, val) ({ unsigned long __tmp; \ argument
198 asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "i"(val)); \
200 asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \
203 #define set_csr(reg, bit) ({ unsigned long __tmp; \ argument
205 asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
[all …]
/libcpu/arm/sep4020/
A Dsep4020.h841 #define write_reg(reg,value) \ argument
844 *(RP)(reg) = value; \
847 #define read_reg(reg) (*(RP)reg) argument

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