Searched refs:set_csr (Results 1 – 8 of 8) sorted by relevance
| /libcpu/risc-v/common64/ |
| A D | riscv_mmu.c | 23 set_csr(sstatus, SSTATUS_SUM); in mmu_enable_user_page_access()
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| A D | tick.c | 54 set_csr(sie, SIP_STIP); in rt_hw_tick_init()
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| A D | encoding.h | 220 #define set_csr(reg, bit) ({ unsigned long __tmp; \ macro
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| /libcpu/risc-v/virt64/ |
| A D | plic.c | 56 set_csr(sie, read_csr(sie) | MIP_SEIP); in plic_irq_enable()
58 set_csr(mie, read_csr(mie) | MIP_MEIP); in plic_irq_enable()
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| /libcpu/risc-v/common/ |
| A D | riscv-ops.h | 26 #define set_csr(reg, bit) ({ unsigned long __tmp; \ macro
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| /libcpu/risc-v/t-head/c906/ |
| A D | plic.c | 138 set_csr(sie, SIE_SEIE); in plic_handle_irq()
219 set_csr(sie, SIE_SEIE); in plic_init()
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| /libcpu/risc-v/t-head/c908/ |
| A D | plic.c | 138 set_csr(sie, SIE_SEIE); in plic_handle_irq()
219 set_csr(sie, SIE_SEIE); in plic_init()
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| /libcpu/risc-v/rv64/ |
| A D | encoding.h | 203 #define set_csr(reg, bit) ({ unsigned long __tmp; \ macro
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