Searched refs:source (Results 1 – 2 of 2) sorted by relevance
| /libcpu/mips/common/ |
| A D | mips_regs.h | 688 #define __read_32bit_c0_register(source, sel) \ argument
692 "mfc0\t%0, " #source "\n\t" \
697 "mfc0\t%0, " #source ", " #sel "\n\t" \
703 #define __read_64bit_c0_register(source, sel) \ argument
708 "dmfc0\t%0, " #source "\n\t" \
714 "dmfc0\t%0, " #source ", " #sel "\n\t" \
767 #define __read_64bit_c0_split(source, sel) \ argument
776 "dmfc0\t%M0, " #source "\n\t" \
785 "dmfc0\t%M0, " #source ", " #sel "\n\t" \
808 "dmtc0\t%L0, " #source "\n\t" \
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| /libcpu/arm/lpc24xx/ |
| A D | start_rvds.S | 1163 LDR R3, =CLKSRCSEL_Val ; Select PLL source clock
1175 ; Wait until PLL Locked (if source is not RTC oscillator)
1180 ; Wait at least 200 cycles (if source is RTC oscillator)
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